HIGH-SPEED 3.3V 70V9279/69S/L 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM Features: True Dual-Ported memory cells which allow simultaneous Full synchronous operation on both ports access of the same memory location 4ns setup to clock and 1ns hold on all control, data, High-speed clock to data access and address inputs Commercial: 7.5/9ns (max.) Data input, address, and control registers Industrial: 7.5ns (max.) Fast 6.5ns clock to data out in the Pipelined output mode Low-power operation Self-timed write allows fast cycle time IDT70V9279/69L 10ns cycle time, 100MHz operation in Pipelined output mode Active: 429mW (typ.) Separate upper-byte and lower-byte controls for Standby: 1.32mW (typ.) multiplexed bus and bus matching compatibility Flow-through or Pipelined output mode on either port via LVTTL- compatible, single 3.3V (0.3V) power supply the FT/PIPE pin Industrial temperature range (40C to +85C) is Counter enable and reset features available for selected speeds Dual chip enables allow for depth expansion without Available in a 128-pin Thin Quad Flatpack (TQFP) package Green parts available, see ordering information additional logic Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R 1 1 CE1L CE1R 0 0 0/1 0/1 LBL LBR OEL OER 1a 0a 0a 1a 1b 0b 0b 1b 0/1 ba 0/1 FT/PIPEL ab FT/PIPER , I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0L-I/O7L I/O0R-I/O7R (1) (1) A14R A14L Counter/ Counter/ A0R A0L MEMORY Address Address CLKR CLKL ARRAY Reg. Reg. ADSR ADSL CNTENR CNTENL CNTRSTL CNTRSTR 3743 drw 01 NOTE: 1. A14X is a NC for IDT70V9269. AUGUST 2019 1 2019 Integrated Device Technology, Inc. DSC 3743/1370V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: With an input data register, the IDT70V9279/69 has been optimized for The IDT70V9279/69 is a high-speed 32/16K x 16 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to applications having unidirectional or bidirectional data flow in bursts. An allow simultaneous access of any address from both ports. Registers on automatic power down feature, controlled by CE0 and CE1, permits the control, data, and address inputs provide minimal setup and hold times. on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices The timing latitude provided by this approach allows systems to be designed with very short cycle times. typically operate on only 429mW of power. (2,3,4) Pin Configuration 1 102 I/O10R N/C I/O9R 2 101 N/C VSS N/C 3 100 99 N/C 4 N/C A9R 5 98 I/O8R A8R 97 N/C 6 A7R 96 N/C 7 A6R 8 95 I/O7R VDD A5R 94 9 A4R 10 93 I/O6R 92 I/O5R A3R 11 A2R 12 91 I/O4R A1R 90 VSS 13 89 I/O3R A0R 14 70V9279/69 88 VDD N/C 15 (5) PKG128 87 I/O2R CNTENR 16 CLKR 86 I/O1R 17 85 I/O0R ADSR 18 128-Pin TQFP VSS 19 84 VSS (6) VDD 83 VDD 20 Top View 82 I/O0L ADSL 21 81 I/O1L CLKL 22 80 VSS CNTENL 23 79 I/O2L N/C 24 78 I/O3L A0L 25 A1L 26 77 VSS 76 I/O4L A2L 27 75 I/O5L A3L 28 A4L 74 29 I/O6L 73 I/O7L A5L 30 72 VDD A6L 31 71 N/C A7L 32 70 N/C A8L 33 69 I/O8L A9L 34 68 N/C N/C 35 67 VDD N/C 36 66 I/O9L N/C 37 65 I/O10L N/C 38 3743 drw 02 NOTES: 1. A14X is a NC for IDT70V9269. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. Package body is approximately 14mm x 20mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.422 A10R 128 A10L 39 127 A11R A11L 40 A12R 126 A12L 41 A13R 125 A13L 42 (1) A14R (1) 124 A14L 43 123 N/C N/C 44 122 N/C N/C 45 121 N/C N/C 46 120 LBR LBL 47 119 UBR UBL 48 CE0R 118 CE0L 49 CE1R 117 CE1L 50 CNTRSTR 116 CNTRSTL 51 VDD 115 VDD 52 VSS 114 VSS 53 R/WR 113 R/WL 54 OER 112 OEL 55 111 FT/PIPER FT/PIPEL 56 110 Vss VSS 57 109 I/O15R I/O15L 58 I/O14R 108 I/O14L 59 107 I/O13R I/O13L 60 106 I/O12R I/O12L 61 VDD 105 VDD 62 VDD 104 VSS 63 103 I/O11R I/O11L 64