7133LA20PFG Renesas

HIGH SPEED 7133SA/LA 2K X 16 DUAL-PORT 7143SA/LA SRAM Features High-speed access MASTER IDT7133 easily expands data bus width to 32 bits Commercial: 20/25/35/45/55/70/90ns (max.) or more using SLAVE IDT7143 Industrial: 25ns (max.) On-chip port arbitration logic (IDT7133 only) Military: 35/55/70/90ns (max.) BUSY output flag on IDT7133 BUSY input on IDT7143 Low-power operation Fully asynchronous operation from either port IDT7133/43SA Battery backup operation2V data retention Active: 1150mW (typ.) TTL-compatible single 5V (10%) power supply Standby: 5mW (typ.) Available in 68-pin ceramic PGA, Flatpack, PLCC and 100- IDT7133/43LA pin TQFP Active: 1050mW (typ.) Military product compliant to MIL-PRF-38535 QML Standby: 1mW (typ.) Industrial temperature range (40C to +85C) is available Versatile control for write: separate write control for lower for selected speeds and upper byte of each port Green parts available, see ordering information Functional Block Diagram R/WLUB R/WRUB CER CEL R/WLLB R/WRLB OER OEL I/O8L-I/O15L I/O8R-I/O15R I/O I/O CONTROL CONTROL I/O0L-I/O7L I/O0R-I/O7R (1) (1) BUSYR BUSYL A10L A10R MEMORY ADDRESS ADDRESS ARRAY DECODER DECODER A0L A0R 11 11 ARBITRATION CER CEL LOGIC (IDT7133 ONLY) 2746 drw 01 NOTE: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input. 1 Jun.16.217133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges address, and I/O pins that permit independent, asynchronous access for Description reads or writes to any location in memory. An automatic power down The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. feature, controlled by CE, permits the on-chip circuitry of each port to enter The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port a very low standby power mode. RAM or as a MASTER Dual-Port RAM together with the IDT7143 Fabricated using CMOS high-performance technology. Low-power SLAVE Dual-Port in 32-bit-or-more word width systems. Using the IDT (LA) versions offer battery backup data retention capability, with each port MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory typically consuming 200W for a 2V battery. system applications results in full-speed, error-free operation without the The IDT7133/7143 devices have identical pinouts. Each is packed in need for additional discrete logic. a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin TQFP. Both devices provide two independent ports with separate control, Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature (1,2,3,4) applications demanding the highest level of performance and reliability. Pin Configurations 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 27 I/O8R 9 I/O8L I/O9R 28 8 I/O7L I/O10R 29 7 I/O6L 30 6 I/O11R I/O5L I/O12R 31 5 I/O4L 32 4 I/O13R I/O3L I/O14R 33 3 I/O2L 7133/43 (4) 34 2 I/O15R PLG68 I/O1L (2) 35 1 GND I/O0L 68-Pin PLCC (1) R/WRUB 36 68 VCC Top View R/WRLB 37 67 R/WLUB 38 66 OER R/WLLB 39 65 A10R OEL A9R 40 64 A10L 41 63 A8R A9L 62 A7R 42 A8L A6R 43 61 A7L 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2746 drw 02 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 A7L 61 43 A6R A8L 62 42 A7R A9L 63 41 A8R 64 A10L 40 A9R 39 OEL 65 A10R R/WLLB 66 38 OER NOTES: R/WLUB 67 7133/43 37 R/WRLB 1. Both VCC pins must be connected to the power supply to ensure reliable (4) (1) FP68 36 VCC 68 R/WRUB operation. 1 35 (2) I/O0L GND 2. Both GND pins must be connected to the ground supply to ensure reliable 68-Pin Flatpack 2 34 I/O1L I/O15R Top View operation. I/O2L 3 33 I/O14R 3. PLG68 package body is approximately 0.95 in x 0.95 in x 0.17 in. I/O3L 4 32 I/O13R FP68 package body is approximately 1.18 in x 1.18 in x 0.16 in. I/O4L 5 31 I/O12R 4. This package code is used to reference the package diagram. 6 30 I/O5L I/O11R 29 I/O6L 7 I/O10R 28 I/O7L 8 I/O9R 27 I/O8L 9 I/O8R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2746 drw 02c 6.42 2 Jun.16.21 A5R I/O7R A4R I/O6R A3R I/O5R A2R I/O4R A1R I/O3R A0R I/O2R BUSYR I/O1R CER I/O0R (2) CEL GND (1) BUSYL VCC A0L I/O15L A1L I/O14L A2L I/O13L A3L I/O12L A4L I/O11L A5L I/O10L A6L I/O9L I/O9L A6L I/O10L A5L I/O11L A4L I/O12L A3L I/O13L A2L I/O14L A1L I/O15L A0L (1) VCC BUSYL (2) GND CEL I/O0R CER I/O1R BUSYR I/O2R A0R I/O3R A1R I/O4R A2R I/O5R A3R I/O6R A4R I/O7R A5R