71342LA25JGI8 Renesas

HIGH SPEED 71342SA/LA 4K X 8 DUAL-PORT STATIC RAM WITH SEMAPHORE Features High-speed access Full on-chip hardware support of semaphore signalling be- Commercial: 20ns(max.) tween ports Industrial: 25ns (max.) Battery backup operation2V data retention (LA only) Low-power operation TTL-compatible single 5V (10%) power supply IDT71342LA Available in plastic packages Active: 700mW (typ.) Industrial temperature range (40C to +85C) is available Standby: 1mW (typ.) for selected speeds Fully asynchronous operation from either port Functional Block Diagram R/WL R/WR CEL CER OEL OER I/O I/O I/O0L-I/O7L I/O0R - I/O7R CONTROL CONTROL MEMORY ARRAY SEMAPHORE LOGIC SEMR SEML ADDRESS ADDRESS A0R-A11R A0L-A11L DECODER DECODER 2721 drw 01 JULY 2019 1 DSC 2621/16 2019 Integrated Device Technology, Inc.71342LA High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges Description The IDT71342 is a high-speed 4K x 8 Dual-Port Static RAM with full time. An automatic power down feature, controlled by CE and SEM, on-chip hardware support of semaphore signalling between the two permits the on-chip circuitry of each port to enter a very low standby power ports. mode (both CE and SEM HIGH). The IDT71342 provides two independent ports with separate Fabricated using CMOS high-performance technology, this device control, address, and I/O pins that permit independent, asynchronous typically operates on only 700mW of power. Low-power (LA) versions access for reads or writes to any location in memory. To assist in offer battery backup data retention capability, with each port typically arbitrating between ports, a fully independent semaphore logic block consuming 200W from a 2V battery. The device is packaged in either a is provided. This block contains unassigned flags which can be 64-pin TQFP or a 52-pin PLCC. accessed by either side however, only one side can control the flag at any (1,2,3) Pin Configurations 20 19 18 17 16 15 14 13 12 11 10 9 8 I/O4L 21 7 A0L I/O5L 6 OEL 22 I/O6L 5 A10L 23 I/O7L 4 A11L 24 3 SEML N/C 25 GND 2 R/WL 26 71342 (4) PLG52 1 I/O0R CEL 27 I/O1R VCC 28 52-PIn PLCC 52 5) Top View I/O2R 29 51 CER I/O3R R/WR 30 50 I/O4R 31 49 SEMR I/O5R A11R 32 48 A10R I/O6R 33 47 34 35 36 37 38 39 40 41 42 43 44 45 46 2721 drw 02a 48 4746 4544 43 4241 40 393837 36 3534 33 32 I/O5R N/C 49 N/C 50 31 I/O4R A10R 51 30 N/C 29 A11R 52 I/O3R SEM R 53 28 I/O2R R/WR 54 27 I/O1R CER 71342 26 55 I/O0R (4) PNG64 25 N/C 56 GND VCC 64-Pin TQFP 24 N/C 57 (5) Top View N/C CEL 58 23 59 22 I/O7L R/WL SEML 60 21 I/O6L A11L 61 20 I/O5L A10L 62 19 I/O4L NOTES: N/C 63 18 N/C 1. All Vcc pins must be connected to power supply. 64 17 N/C I/O3L 2. All GND pins must be connected to ground supply. 101112 131415 16 1 2 3 4 5 6 7 8 9 3. PLG52 package body is approximately .79 in x .79 in x .17 in. PNG64 package body is approximately 14mm x 14mm x 1.4mm. 2721 drw 03a 4. This package code is used to reference the package diagram. 6.422 I/O7R I/O3L N/C I/O2L A9R I/O1L A8R I/O0L A7R A9L A6R A8L A5R A7L A4R A6L A3R A5L A2R A4L A1R A3L A0R A2L OER A1L OEL OER A0L A0R A1L A1R A2L A2R A3L A3R A4L A4R A5L A5R A6L A6R N/C N/C A7L A7R A8L A8R A9L A9R N/C N/C I/O0L N/C I/O1L I/O7R I/O2L I/O6R