IDT72125 CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16 The ability to buffer wide word widths (x16) make these FIFOs ideal for laser FEATURES: printers, FAX machines, local area networks (LANs), video storage and disk/ 25ns parallel port access time, 35ns cycle time tape controller applications. 50MHz serial shift frequency Expansion in width and depth can be achieved using multiple chips. IDTs Wide x16 organization offering easy expansion unique serial expansion logic makes this possible using a minimum of pins. Low power consumption (50mA typical) The unique serial output port is driven by one data pin (SO) and one clock Least/Most Significant Bit first read selected by asserting the pin (SOCP). The Least Significant or Most Significant Bit can be read first by FL/DIR pin programming the DIR pin after a reset. Four memory status flags: Empty, Full, Half-Full, and Almost- Monitoring the FIFO is eased by the availability of four status flags: Empty, Empty/Almost-Full Full, Half-Full and Almost-Empty/Almost-Full. The Full and Empty flags prevent Dual-Port zero fall-through architecture any FIFO data overflow or underflow conditions. The Half-Full Flag is available Available in 28-pin 300 mil plastic DIP and 28-pin SOIC in both single and expansion mode configurations. The Almost-Empty/Almost- Green parts available, see ordering information Full Flag is available only in a single device mode. The IDT72125 is fabricated using submicron CMOS technology. DESCRIPTION: The IDT72125 is a high-speed, low- power, dedicated, parallel-to-serial FIFO. This FIFO features a 16-bit parallel input port and a serial output port with 1,024 word depths, respectively. FUNCTIONAL BLOCK DIAGRAM D0-15 W RS 16 RESET LOGIC RAM WRITE READ ARRAY POINTER POINTER 1,024 x 16 FF RSIX EXPANSION FLAG EF RSOX LOGIC LOGIC HF FL/DIR AEF SERIAL OUTPUT LOGIC 2665 drw01 SOCP SO IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE FEBRUARY 2016 1 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2665/1IDT72125 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGE 1,024 x 16 PIN CONFIGURATION 28 W 1 Vcc 27 D0 2 D15 26 D1 3 D14 25 D2 4 D13 24 D3 5 D12 23 D4 D11 6 22 D5 7 D10 21 D6 D9 8 20 D7 9 D8 19 RS EF 10 18 FF 11 SO 17 HF 12 SOCP 16 13 RSOX/AEF RSIX 15 14 GND FL/DIR 2665 drw 02 PLASTIC THIN DIP (P28, order code: TP) SOIC (SO28, order code: SO) TOP VIEW PIN DESCRIPTIONS Symbol Name I/O Description D0D15 Inputs I Data inputs for 16-bit wide data. RS Reset I When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array. FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE after power-up. W must be high during the RS cycle. Also the First Load pin (FL) is programmed only during Reset. W Write I A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation. SOCP Serial Output Clock I A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together. FL/DIR First Load/Direction I This is a dual purpose input used in the width and depth expansion configurations. The First Load (FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first device to be loaded with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the Least Significant or Most Significant bit first. RSIX Read Serial In I In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX Expansion is connected to RSOX (expansion out) of the previous device. SO Serial Output O Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the Direction pin programming. During Expansion the SO pins are tied together. FF Full Flag O When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH, the device is not full. EF Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the device is not empty. HF Half-Full Flag O When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to half-full. RSOX/AEF Read Serial O This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEF output pin. Out Expansion When AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When AEF is HIGH, the device Almost-Empty, is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX connected to RSIX of the next device) a Almost-Full Flag pulse is sent from RSOX to RSIX to coordinate the width, depth or daisy chain expansion. VCC Power Supply Single power supply of 5V. GND Ground Single ground of 0V. 2