CY7C419/21/25/29/33256/512/1K/2K/4K x 9 Asynchronous FIFO CY7C419/21/25/29/33 256/512/1K/2K/4K x 9 Asynchronous FIFO Features Functional Description Asynchronous First-In First-Out (FIFO) Buffer Memories The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and CY7C432/3 are first-in first-out (FIFO) memories offered in 256 x 9 (CY7C419) 600-mil wide and 300-mil wide packages. There are 256, 512, 512 x 9 (CY7C421) 1,024, 2,048, and 4,096 words respectively by 9 bits wide. Each 1K x 9 (CY7C425) FIFO memory is organized such that the data is read in the same 2K x 9 (CY7C429) sequential order that it was written. Full and empty flags are 4K x 9 (CY7C433) provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, Dual-Ported RAM Cell or both. The depth expansion technique steers the control High Speed 50 MHz Read and Write Independent of Depth and signals from one device to another in parallel. This eliminates the Width serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. Low Operating Power: I = 35 mA CC The read and write operations may be asynchronous each can Empty and Full Flags (Half Full Flag in Standalone) occur at a rate of 50 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. TTL Compatible The nine data outputs go to the high impedance state when R is Retransmit in Standalone HIGH. Expandable in Width A Half Full (HF) output flag that is valid in the standalone and width expansion configurations is provided. In the depth PLCC, 7x7 TQFP, SOJ, 300-mil, and 600-mil DIP expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it is Pb-free Packages Available activated. Pin Compatible and Functionally Equivalent to IDT7200, In the standalone and width expansion configurations, a LOW on IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, the retransmit (RT) input causes the FIFOs to retransmit the AM7202, AM7203, and AM7204 data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000V and latch up is prevented by careful layout and guard rings. Table 1. Selection Guide 4K x 9 10 15 20 25 30 40 65 Frequency (MHz) 50 40 33.3 28.5 25 20 12.5 Maximum Access Time (ns) 10 15 20 25 30 40 65 I (mA) 35 35 35 35 35 35 35 CC1 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-06001 Rev. *D Revised June 03, 2009 + Feedback + Feedback + Feedback CY7C419/21/25/29/33 Logic Block Diagram DATA INPUTS (D D ) 0 8 WRITE W RAM ARRAY CONTROL 256x 9 512x 9 WRITE 1024x 9 READ POINTER 2048x 9 POINTER 4096x 9 THREE- STATE BUFFERS DATA OUTPUTS (Q Q ) 0 8 MR RESET LOGIC FL/RT READ R CONTROL FLAG EF LOGIC FF EXPANSION LOGIC XI XO/HF Pin Configurations Figure 1. 32-Pin PLCC/LCC (Top View) Figure 2. 28-Pin DIP (Top View) Figure 3. 32-PIn TQFP (Top View) 1 28 V W cc 2 27 D D 8 4 32 3130 29 28 27 26 25 4 3 2 1 323130 3 26 D D D 3 5 2 D D 5 29 6 7 D 1 24 1 4 D 25 D 2 6 D D 1 6 28 7 FL/RT D 0 2 23 5 D 24 D NC 1 D 7 27 7 0 7C419 NC NC 3 22 6 D 23 FL/RT XI FL/RT 0 8 26 7C420/1 7C419 7C419 7 22 NC 4 21 NC XI 7C424/5 MR FF 9 7C421/5/9 25 MR 7C421/5/9 7C428/9 XI FF 8 21 5 20 MR 7C433 EF 7C433 Q EF 0 10 24 7C432/3 Q FF 9 20 EF 0 XO/HF 6 19 Q 1 11 23 XO/HF 10 Q 19 Q Q NC Q 1 0 XO/HF 12 22 7 7 7 18 11 Q 18 Q Q Q2 Q 2 6 1 Q 13 21 6 8 17 7 14 15 1617 181920 Q 12 Q 3 17 5 9 101112131415 16 Q 13 16 Q 8 4 14 15 GND R Document : 38-06001 Rev. *D Page 2 of 16 + Feedback + Feedback + Feedback Q D 3 3 Q D 8 8 GND W NC NC R V cc Q D 4 4 Q D 5 5 Q D 2 2 Q 3 D 3 Q 8 D 8 GND W R V CC Q 4 D 4 Q 5 D 5 Q D 6 6