TM CMOS SyncFIFO IDT72205LB, IDT72215LB, IDT72225LB, IDT72235LB, 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72245LB LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 write controls. These FIFOs are applicable for a wide variety of data buffering FEATURES: needs, such as optical disk controllers, Local Area Networks (LANs), and 256 x 18-bit organization array (IDT72205LB) interprocessor communication. 512 x 18-bit organization array (IDT72215LB) These FIFOs have 18-bit input and output ports. The input port is controlled 1,024 x 18-bit organization array (IDT72225LB) by a free-running clock (WCLK), and an input enable pin (WEN). Data is read 2,048 x 18-bit organization array (IDT72235LB) into the synchronous FIFO on every clock when WEN is asserted. The output 4,096 x 18-bit organization array (IDT72245LB) port is controlled by another clock pin (RCLK) and another enable pin (REN). 10 ns read/write cycle time The read clock can be tied to the write clock for single clock operation or the Empy and Full flags signal FIFO status two clocks can run asynchronous of one another for dual-clock operation. An Easy expandable in depth and width Output Enable pin (OE) is provided on the read port for three-state control of Asynchronous or coincident read and write clocks the output. Programmable Almost-Empty and Almost-Full flags with The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF), default settings and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The Half-Full flag capability offset loading of the programmable flags is controlled by a simple state machine, Dual-Port zero fall-through time architecture and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available Output enable puts output data bus in high-impedence state when the FIFO is used in a single device configuration. High-performance submicron CMOS technology These devices are depth expandable using a Daisy-Chain technique. The Available in a 64-lead thin quad flatpack (TQFP/STQFP) XI and XO pins are used to expand the FIFOs. In depth expansion configu- and plastic leaded chip carrier (PLCC) ration, First Load (FL) is grounded on the first device and set to HIGH for all Industrial temperature range (40C to +85C) is available other devices in the Daisy Chain. Green parts available, see ordering information The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated using high-speed submicron CMOS technology. DESCRIPTION: The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high speed, low-power First-In, First-Out (FIFO) memories with clocked read and FUNCTIONAL BLOCK DIAGRAM WCLK D0-D17 INPUT REGISTER OFFSET REGISTER FLAG WRITE CONTROL LOGIC LOGIC RAM ARRAY /( ) 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 4,096 x 18 READ POINTER WRITE POINTER READ CONTROL LOGIC EXPANSION LOGIC ( )/ OUTPUT REGISTER RESET LOGIC 2766 drw 01 Q0-Q17 RCLK IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. NOVEMBER 2017 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2766/4TM COMMERCIAL AND INDUSTRIAL IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 TEMPERATURE RANGES PIN CONFIGURATIONS 9 8 7 6 5 4 3 2 6867666564636261 VCC D14 10 60 1 D13 11 Q14 59 D12 12 58 Q13 57 GND D11 13 D10 14 56 Q12 D9 15 55 Q11 54 VCC VCC 16 D8 17 53 Q10 GND 18 52 Q9 51 GND D7 19 D6 20 50 Q8 Q7 D5 21 49 22 48 VCC D4 D3 23 Q6 47 Q5 D2 24 46 D1 25 GND 45 D0 44 Q4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 2766 drw 02 PLCC (J68-1, order code: J) TOP VIEW PIN 1 D15 1 48 Q14 D14 2 47 Q13 D13 3 GND 46 D12 4 Q12 45 D11 5 Q11 44 D10 6 VCC 43 D9 Q10 7 42 D8 Q9 8 41 D7 GND 9 40 D6 Q8 10 39 D5 Q7 11 38 D4 12 37 Q6 D3 13 Q5 36 D2 14 GND 35 D1 15 Q4 34 D0 16 33 VCC 2766 drw 03 TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW 2 MARCH 2013 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PAE D15 D16 FL D16 D17 D17 WCLK WCLK GND WEN GND RCLK WXI RCLK VCC REN VCC PAF LD RXI OE RS FF VCC WXO/HF VCC / GND RXO GND EF Q0 Q0 Q17 Q1 VCC Q16 Q1 Q17 GND GND GND Q16 Q15 Q2 Q2 Q3 GND Q3 VCC Q15 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32