TM CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, IDT723624 IDT723634 512 x 36 x 2, 1,024 x 36 x 2 IDT723644 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Serial or parallel programming of partial flags FEATURES: Port B bus sizing of 36-bits (long word), 18-bits (word) and Memory storage capacity: 9-bits (byte) IDT723624 256 x 36 x 2 Big- or Little-Endian format for word and byte bus sizes IDT723634 512 x 36 x 2 Master Reset clears data and configures FIFO, Partial Reset IDT723644 1,024 x 36 x 2 clears data but retains configuration settings Clock frequencies up to 67 MHz (10 ns access time) Mailbox bypass registers for each FIFO Two independent clocked FIFOs buffering data in opposite Free-running CLKA and CLKB may be asynchronous or coinci- directions dent (simultaneous reading and writing of data on a single clock Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags edge is permitted) functions) or First Word Fall Through Timing (using ORA, ORB, Auto power down minimizes power dissipation IRA, and IRB flag functions) Available in space saving 128-pin Thin Quad Flatpack (TQFP) Programmable Almost-Empty and Almost-Full flags each has Green parts available, see ordering information three default offsets (8, 16 and 64) FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register CLKA CSA Port-A Control W/RA RAM ARRAY Logic ENA 36 36 256 x 36 MBA 512 x 36 1,024 x 36 36 FIFO1, MRS1 Mail1 Reset PRS1 Write Read Logic Pointer Pointer 36 Status Flag EFB/ORB FFA/IRA Logic AEB AFA FIFO1 SPM Programmable Flag Timing FS0/SD FWFT Offset Registers Mode FS1/SEN A0-A35 B0-B35 10 FIFO2 EFA/ORA Status Flag FFB/IRB AEA Logic AFB 36 Read Write Pointer Pointer 36 FIFO2, MRS2 Mail2 Reset PRS2 Logic RAM ARRAY 36 256 x 36 36 512 x 36 CLKB 1,024 x 36 CSB W/RB Port-B ENB Control Mail 2 MBB Logic Register BE BM MBF2 SIZE 3270 drw01 IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MARCH 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3270/6 Input Output Register Register Input Bus- Output Bus- Matching Matching Input Output Register RegisterIDT723624/723634/723644 CMOS SyncBiFIFO WITH BUS-MATCHING COMMERCIAL TEMPERATURE RANGE 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 These devices are a synchronous (clocked) FIFO, meaning each port DESCRIPTION: employs a synchronous interface. All data transfers through a port are gated The IDT723624/723634/723644 is a monolithic, high-speed, low- to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for power, CMOS bidirectional synchronous (clocked) FIFO memory which each port are independent of one another and can be asynchronous or supports clock frequencies up to 67 MHz and has read access times as fast as coincident. The enables for each port are arranged to provide a simple 10 ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board bidirectional interface between microprocessors and/or buses with syn- each chip buffer data in opposite directions. FIFO data on Port B can be input chronous control. and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations. PIN CONFIGURATION INDEX W/RA 102 CLKB 1 ENA 101 PRS2 2 CLKA 100 Vcc 3 GND 99 B35 4 A35 98 B34 5 A34 97 B33 6 A33 96 B32 7 A32 95 GND 8 Vcc 94 GND 9 93 A31 B31 10 92 A30 B30 11 91 GND B29 12 90 A29 13 B28 89 A28 14 B27 88 B26 A27 15 87 Vcc A26 16 86 B25 A25 17 85 B24 A24 18 84 BM A23 19 83 GND BE/FWFT 20 82 B23 GND 21 81 B22 A22 22 80 B21 Vcc 23 79 B20 A21 24 78 A20 25 B19 77 26 B18 A19 76 GND 27 A18 75 B17 28 GND 74 B16 29 A17 73 SIZE A16 30 72 Vcc A15 31 71 B15 32 A14 70 B14 33 A13 69 B13 34 Vcc 68 B12 A12 35 67 GND GND 36 37 66 B11 A11 B10 38 65 A10 3270 drw02 TQFP (PK128-1, order code: PF) TOP VIEW 2 A9 39 128 CSA A8 40 127 FFA/IRA A7 41 126 EFA/ORA A6 42 125 PRS1 GND 43 124 Vcc A5 44 123 AFA A4 45 122 AEA A3 46 121 MBF2 SPM 47 120 MBA Vcc 48 119 MRS1 A2 49 118 FS0/SD A1 50 117 GND A0 51 116 GND GND 52 115 FS1/SEN B0 53 114 MRS2 MBB B1 54 113 MBF1 B2 55 112 Vcc B3 56 111 AEB 110 B4 57 AFB 109 B5 58 EFB/ORB 108 GND 59 FFB/IRB 107 B6 60 GND 106 Vcc 61 CSB 105 B7 62 W/RB 104 B8 63 ENB 103 B9 64