TM CMOS SyncBiFIFO IDT723622 256 x 36 x 2, 512 x 36 x 2, IDT723632 1,024 x 36 x 2 IDT723642 Fast access times of 10ns FEATURES: Available in space-saving 120-pin Thin Quad Flatpack (TQFP) Memory storage capacity: Green parts available IDT723622 256 x 36 x 2 IDT723632 512 x 36 x 2 DESCRIPTION: IDT723642 1,024 x 36 x 2 Free-running CLKA and CLKB may be asynchronous or The IDT723622/723632/723642 are a monolithic, high-speed, low-power, coincident (simultaneous reading and writing of data on a single CMOS Bidirectional SyncFIFO (clocked) memory which supports clock fre- clock edge is permitted) quencies up to 66.7MHz and have read access times as fast as 10ns. Two independent clocked FIFOs buffering data in opposite Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board directions each chip buffer data in opposite directions. Communication between Mailbox bypass register for each FIFO each port may bypass the FIFOs via two 36-bit mailbox registers. Each Programmable Almost-Full and Almost-Empty flags mailbox register has a flag to signal when new mail has been stored. Microprocessor Interface Control Logic These devices are a synchronous (clocked) FIFO, meaning each port IRA, ORA, AEA, and AFA flags synchronized by CLKA employs a synchronous interface. All data transfers through a port are gated IRB, ORB, AEB, and AFB flags synchronized by CLKB to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for Supports clock frequencies up to 66.7MHz each port are independent of one another and can be asynchronous or FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register CLKA Port-A CSA Control W/RA RAM Logic ENA ARRAY MBA 256 x 36 512 x 36 36 1,024 x 36 FIFO1, Mail1 RST1 Reset Logic Write Read Pointer Pointer 36 Status Flag ORB IRA Logic AFA AEB FIFO 1 Programmable Flag FS0 Offset Registers B0 - B35 FS1 A0 - A35 10 FIFO 2 ORA Status Flag IRB Logic AEA AFB 36 Read Write Pointer Pointer 36 FIFO2, Mail2 RST2 Reset Logic RAM ARRAY 256 x 36 512 x 36 CLKB Port-B 1,024 x 36 CSB Control W/RB Logic ENB Mail 2 MBB Register 3022 drw 01 MBF2 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. FEBRUARY 2015 COMMERCIAL TEMPERATURE RANGE 1 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3022/6 Input Output Register Register Output Input Register RegisterIDT723622/723632/723642 CMOS SyncBiFIFO COMMERCIAL TEMPERATURE RANGE 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 two-stage synchronized to the port clock that reads data from its array. Offset DESCRIPTION (CONTINUED) values for the Almost-Full and Almost-Empty flags of both FIFOs can be coincident. The enables for each port are arranged to provide a simple programmed from Port A. bidirectional interface between microprocessors and/or buses with syn- Two or more devices may be used in parallel to create wider data paths. chronous control. If, at any time, the FIFO is not actively performing a function, the chip will Each FIFO has a programmable Almost-Empty flag (AEA and AEB) automatically power down. During the power down state, supply current and a progammable Almost-Full flag (AFA and AFB). AEA and AEB consumption (ICC) is at a minimum. Initiating any operation (by activating control indicate when a selected number of words remain in the FIFO memory. inputs will immediately take the device out of the power down state. AFA and AFB indicate when the FIFO contains more than a selected The 723622/723632/723642 are characterized for operation from number of words. 0C to 70C. They are fabricated using high speed, submicron CMOS The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB) flags of a FIFO technology. are two-stage synchronized to the port clock that writes data into its array. The Output Ready (ORA, ORB) and Almost-Empty (AEA, AEB) flags of a FIFO are PIN CONFIGURATION B35 A35 90 1 B34 A34 89 2 B33 A33 88 3 B32 87 A32 4 GND VCC 86 5 B31 A31 85 6 B30 84 A30 7 B29 GND 83 8 B28 A29 82 9 B27 81 A28 10 B26 A27 80 11 VCC A26 79 12 B25 A25 78 13 B24 A24 77 14 GND 76 A23 15 B23 GND 75 16 B22 A22 74 17 B21 73 VCC 18 B20 A21 72 19 B19 A20 71 20 B18 70 A19 21 GND A18 69 22 B17 68 GND 23 B16 67 A17 24 VCC A16 66 25 B15 65 A15 26 B14 64 A14 27 B13 A13 63 28 B12 62 VCC 29 GND 61 A12 30 3022 drw 03 TQFP (PNG120, order code: PF) TOP VIEW 2 GND 120 31 GND A11 119 CLKA 32 A10 ENA 33 118 A9 34 W/RA 117 A8 35 116 CSA A7 36 IRA 115 A6 37 ORA 114 GND 38 113 VCC A5 39 112 AFA A4 40 111 AEA A3 41 110 MBF2 VCC 42 109 MBA A2 RST1 43 108 A1 44 107 FS0 A0 45 GND 106 GND 46 105 FS1 B0 104 RST2 47 B1 48 103 MBB B2 102 49 MBF1 B3 50 101 VCC B4 100 51 AEB B5 52 99 AFB GND 98 53 ORB B6 54 97 IRB VCC 55 96 GND B7 95 56 CSB B8 57 94 W/RB 58 B9 93 ENB B10 59 92 CLKB B11 91 60 VCC