3.3 VOLT CMOS SyncFIFO IDT72V201, IDT72V211 256 x 9, 512 x 9, IDT72V221, IDT72V231 1,024 x 9, 2,048 x 9, IDT72V241, IDT72V251 4,096 x 9 and 8,192 x 9 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 are very high-speed, low-power First-In, First-Out (FIFO) memories with FEATURES: clocked read and write controls. The architecture, functional operation and pin 256 x 9-bit organization IDT72V201 assignments are identical to those of the IDT72201/72211/72221/72231/ 512 x 9-bit organization IDT72V211 72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and 1,024 x 9-bit organization IDT72V221 3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9- 2,048 x 9-bit organization IDT72V231 bit memory array, respectively. These FIFOs are applicable for a wide variety 4,096 x 9-bit organization IDT72V241 of data buffering needs such as graphics, local area networks and interprocessor 8,192 x 9-bit organization IDT72V251 communication. 10 ns read/write cycle time These FIFOs have 9-bit input and output ports. The input port is 5V input tolerant controlled by a free-running clock (WCLK), and two Write Enable pins Read and Write clocks can be independent (WEN1, WEN2). Data is written into the Synchronous FIFO on every Dual-Ported zero fall-through time architecture rising clock edge when the Write Enable pins are asserted. The output Empty and Full Flags signal FIFO status port is controlled by another clock pin (RCLK) and two Read Enable pins Programmable Almost-Empty and Almost-Full flags can be set to (REN1, REN2). The Read Clock can be tied to the Write Clock for single any depth clock operation or the two clocks can run asynchronous of one another Programmable Almost-Empty and Almost-Full flags default to for dual-clock operation. An Output Enable pin (OE) is provided on the Empty+7, and Full-7, respectively read port for three-state control of the output. Output Enable puts output data bus in high-impedance state The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF). Advanced submicron CMOS technology Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin provided for improved system control. The programmable flags default to plastic Thin Quad FlatPack (TQFP) Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag Industrial temperature range (40C to +85C) is available offset loading is controlled by a simple state machine and is initiated by asserting Green parts available, see ordering information the Load pin (LD). These FIFOs are fabricated using high-speed submicron CMOS DESCRIPTION: technology. The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs FUNCTIONAL BLOCK DIAGRAM D0 - D8 WCLK LD WEN1 WEN2 INPUT REGISTER OFFSET REGISTER EF FLAG PAE WRITE CONTROL LOGIC LOGIC PAF FF RAM ARRAY 256 x 9, 512 x 9, WRITE POINTER READ POINTER 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 READ CONTROL LOGIC OUTPUT REGISTER RESET LOGIC RCLK REN1 REN2 RS OE 4092 drw 01 Q0 - Q8 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2018 1 DSC-4092/7IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 TEMPERATURE RANGES PIN CONFIGURATION INDEX INDEX 32 31 30 29 28 27 26 25 432 32 31 30 1 5 29 D1 RS D1 1 WEN1 24 D0 6 28 WEN1 D0 2 WCLK 23 PAF 7 27 WCLK PAF 3 22 WEN2/LD PAE 8 26 WEN2/LD 4 PAE 21 VCC GND 9 25 VCC 5 GND 20 Q8 REN1 10 24 Q8 6 REN1 19 Q7 11 23 RCLK Q7 RCLK 7 18 Q6 REN2 12 22 Q6 17 REN2 8 Q5 OE 13 21 Q5 9 10111213 1415 16 14 15 16 17 18 19 20 4092 drw02 4092 drw02a TQFP (PR32-1, order code: PF) PLCC (J32-1, order code: J) TOP VIEW TOP VIEW PIN DESCRIPTIONS Symbol Name I/O Description D0-D8 Data Inputs I Data inputs for a 9-bit bus. RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. WEN1 Write Enable 1 I If the FIFO is configured to have programmable flags, WEN1 is the only Write Enable pin. When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. WEN2/LD Write Enable 2/ I The FIFO is configured at Reset to have either two write enables or programmable flags. If WEN2/LD Load is HIGH at Reset, this pin operates as a second write enable. If WEN2/LD is LOW at Reset, this pin operates as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Q0-Q8 Data Outputs O Data outputs for a 9-bit bus. RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted. REN1 Read Enable 1 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. REN2 Read Enable 2 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. COMMERCIAL AND INDUSTRIAL Data will not be read from the FIFO if the EF is LOW. TEMPERATURE RANGES OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. PAE Programmable O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default Almost-Empty Flag offset at reset is Empty+7. PAE is synchronized to RCLK. PAF Programmable O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default Almost-Full Flag offset at reset is Full-7. PAF is synchronized to WCLK. FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. VCC Power One 3.3V volt power supply pin. GND Ground One 0 volt ground pin. 2 D2 OE D3 EF FF D4 Q0 D5 Q1 D6 Q2 D7 Q3 D8 Q4 RS D2 EF D3 FF D4 Q0 D5 Q1 D6 Q2 D7 Q3 D8 Q4