3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 IDT72V261LA 32,768 x 9 IDT72V271LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: Program partial flags by either serial or parallel means Choose among the following memory organizations: Select IDT Standard timing (using EF and FF flags) or First IDT72V261LA 16,384 x 9 Word Fall Through timing (using OR and IR flags) IDT72V271LA 32,768 x 9 Output enable puts data outputs into high impedance state Pin-compatible with the IDT72V281/72V291 and IDT72V2101/ Easily expandable in depth and width 72V2111SuperSync FIFOs Independent Read and Write clocks (permit reading and writing Functionally compatible with the 5 Volt IDT72261/72271 family simultaneously) 10ns read/write cycle time (6.5ns access time) Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- Fixed, low first word data latency time pin Slim Thin Quad Flat Pack (STQFP) 5V input tolerant High-performance submicron CMOS technology Auto power down minimizes standby power consumption Industrial temperature range (40C to +85C) is available Master Reset clears entire FIFO Green parts available, see ordering information Partial Reset clears data, but retains programmable settings Retransmit operation with fixed, low first word data DESCRIPTION: latency time The IDT72V261LA/72V271LA are functionally compatible versions of Empty, Full and Half-Full flags signal FIFO status the IDT72261/72271 designed to run off a 3.3V supply for very low power Programmable Almost-Empty and Almost-Full flags, each flag consumption. The IDT72V261LA/72V271LA are exceptionally deep, high can default to one of two preselected offsets speed, CMOS First-In-First-Out (FIFO) memories with clocked read and FUNCTIONAL BLOCK DIAGRAM D0 -D8 WEN WCLK LD SEN OFFSET REGISTER INPUT REGISTER FF/IR PAF FLAG EF/OR WRITE CONTROL LOGIC PAE LOGIC HF FWFT/SI RAM ARRAY 16,384 x 9 WRITE POINTER 32,768 x 9 READ POINTER READ CONTROL RT LOGIC OUTPUT REGISTER MRS RESET RCLK LOGIC PRS REN Q0 -Q8 4673 drw 01 OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEBRUARY 2018 1 DSC-4673/6IDT72V261LA/72V271LA COMMERCIAL AND INDUSTRIAL 3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9 TEMPERATURE RANGES SuperSync FIFOs are particularly appropriate for network, video, tele- DESCRIPTION (CONTINUED) communications, data communications and other applications that need to write controls. These FIFOs offer numerous improvements over previous buffer large amounts of data. SuperSync FIFOs, including the following: The input port is controlled by a Write Clock (WCLK) input and a Write The limitation of the frequency of one clock input with respect to the Enable (WEN) input. Data is written into the FIFO on every rising edge of other has been removed. The Frequency Select pin (FS) has been WCLK when WEN is asserted. The output port is controlled by a Read removed, thus it is no longer necessary to select which of the two clock Clock (RCLK) input and Read Enable (REN) input. Data is read from the inputs, RCLK or WCLK, is running at the higher frequency. FIFO on every rising edge of RCLK when REN is asserted. An Output The period required by the retransmit operation is now fixed and short. Enable (OE) input is provided for three-state control of the outputs. The first word data latency period, from the time the first word is written The frequencies of both the RCLK and the WCLK signals may vary from to an empty FIFO to the time it can be read, is now fixed and short. 0 to fMAX with complete independence. There are no restrictions on the (The variable clock cycle counting delay associated with the latency frequency of one clock input with respect to the other. period found on previous SuperSync devices has been eliminated on this SuperSync family.) PIN CONFIGURATIONS PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (3) WEN DNC 1 48 (3) DNC SEN 2 47 (1) DC GND 3 46 (3) VCC DNC 4 45 (3) VCC 5 44 DNC (2) VCC GND 6 43 (3) (2) DNC GND 7 42 (3) (2) GND 8 41 DNC (2) (3) GND 9 40 DNC (2) GND GND 10 39 (3) (2) 11 38 DNC GND (3) (2) GND 12 37 DNC (2) Q8 GND 13 36 (2) Q7 GND 14 35 15 34 Q6 D8 16 33 GND D7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4673 drw 02 TQFP (PN64, ORDER CODE: PF) STQFP (PP64, ORDER CODE: TF) TOP VIEW NOTES: 1. DC = Dont Care. Must be tied to GND or VCC, cannot be left open. 2. This pin may either be tied to ground or left open. 3. DNC = Do Not Connect. 2 WCLK PRS D5 MRS D4 D3 LD D2 FWFT/SI D1 GND D0 FF/IR PAF GND Q0 HF Q1 VCC PAE GND EF/OR Q2 Q3 RCLK REN VCC RT Q4 OE Q5 D6