TM 3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING 256 x 36 IDT72V3623 1,024 x 36 IDT72V3643 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Reset clears data and configures FIFO, Partial Reset clears FEATURES: data but retains configuration settings Memory storage capacity: Mailbox bypass registers for each FIFO IDT72V3623256 x 36 Free-running CLKA and CLKB may be asynchronous or IDT72V36431,024 x 36 coincident (simultaneous reading and writing of data on a single Clock frequencies up to 100 MHz (6.5 ns access time) clock edge is permitted) Clocked FIFO buffering data from Port A to Port B Easily expandable in width and depth IDT Standard timing (using EF and FF) or First Word Fall Auto power down minimizes power dissipation Through Timing (using OR and IR flag functions) Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Programmable Almost-Empty and Almost-Full flags each has Pin and functionally compatible versions of the 5V operating three default offsets (8, 16 and 64) IDT723623/723643 Serial or parallel programming of partial flags Industrial temperature range (40C to +85C) is available Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits Green parts available, see ordering information (byte) Big- or Little-Endian format for word and byte bus sizes FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register CLKA CSA Port-A W/RA Control ENA Logic MBA 36 RAM ARRAY 36 36 FIFO1 RS1 256 x 36 Mail1, 1,024 x 36 RS2 Mail2, Reset PRS Logic 36 Write Read Pointer Pointer A0-A35 B0-B35 Status Flag FF/IR EF/OR Logic AF AE 36 36 SPM Programmable Flag Timing FS0/SD FWFT Offset Registers Mode FS1/SEN 10 CLKB CSB W/RB Port-B ENB Control MBB Logic BE BM Mail 2 SIZE Register 4662 drw01 MBF2 IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. MARCH 2018 COMMERCIAL TEMPERATURE RANGE 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4662/8 Input Register Bus- Matching Output Register TM IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO WITH BUS-MATCHING COMMERCIAL TEMPERATURE RANGE 256 x 36, 1,024 x 36 read access times as fast as 6.5 ns. The 256/1,024 x 36 dual-port SRAM DESCRIPTION: FIFO buffers data from Port A to Port B. FIFO data on Port B can output The IDT72V3623/72V3643 are pin and functionally compatible in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian versions of the IDT723623/723643, designed to run off a 3.3V supply for configurations. exceptionally low power consumption. These devices are monolithic, These devices are synchronous (clocked) FIFOs, meaning each port high-speed, low-power, CMOS unidirectional Synchronous (clocked) employs a synchronous interface. All data transfers through a port are gated FIFO memory which supports clock frequencies up to 100 MHz and has PIN CONFIGURATION INDEX 1 CLKB W/RA 102 2 ENA VCC 101 3 VCC CLKA 100 4 GND B35 99 5 B34 A35 98 6 A34 B33 97 7 B32 A33 96 8 GND A32 95 9 Vcc 94 GND 10 B31 A31 93 11 A30 92 B30 GND 12 B29 91 13 A29 90 B28 14 89 B27 A28 15 B26 A27 88 16 87 VCC A26 17 A25 86 B25 18 85 B24 A24 19 A23 84 BM 20 83 GND BE/FWFT 21 82 B23 GND 22 81 B22 A22 23 80 B21 VCC 24 79 A21 B20 25 78 B19 A20 26 77 A19 B18 27 76 GND A18 GND 28 75 B17 29 74 B16 A17 A16 30 73 SIZE 31 72 VCC A15 32 71 B15 A14 33 70 B14 A13 69 34 B13 VCC 35 68 B12 A12 67 36 GND GND 37 66 B11 A11 65 38 B10 A10 4662 drw02 TQFP (PK128, order code: PF) NOTE: TOP VIEW 1. NC no internal connection 2 CSA 39 128 A9 127 FF/IR 40 A8 126 NC 41 A7 125 PRS 42 A6 124 VCC 43 GND 123 AF 44 A5 45 122 NC A4 121 MBF2 46 A3 47 120 MBA SPM 119 RS1 48 VCC 118 49 FS0/SD A2 50 117 GND A1 51 116 GND A0 52 115 FS1/SEN GND 53 114 RS2 B0 54 113 MBB B1 55 112 B2 MBF1 56 111 B3 VCC 57 110 B4 AE 58 109 B5 NC 59 108 GND EF/OR 60 107 B6 NC 61 106 VCC GND 62 105 B7 CSB 63 104 W/RB B8 103 64 ENB B9