CY7C4425/4205/4215
CY7C4225/4235/4245
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Features Functional Description
High speed, low power, first-in first-out (FIFO) memories The CY7C42X5 are high speed, low power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All are
64 x 18 (CY7C4425)
18 bits wide and are pin/functionally compatible to IDT722X5.
The CY7C42X5 can be cascaded to increase FIFO depth.
256 x 18 (CY7C4205)
Programmable features include Almost Full/Almost Empty flags.
512 x 18 (CY7C4215)
These FIFOs provide solutions for a wide variety of data
buffering needs, including high speed data acquisition, multipro-
1K x 18 (CY7C4225)
cessor interfaces, and communications buffering.
2K x 18 (CY7C4235)
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
4K x 18 (CY7C4245)
is controlled by a free-running clock (WCLK) and a write enable
High speed 100 MHz operation (10 ns read/write cycle time)
pin (WEN). When WEN is asserted, data is written into the FIFO
on the rising edge of the WCLK signal. While WEN is held active,
Low power (I = 45 mA)
CC
data is continually written into the FIFO on each cycle. The
Fully asynchronous and simultaneous read and write operation output port is controlled in a similar manner by a free-running
read clock (RCLK) and a read enable pin (REN). In addition, the
Empty, Full, Half Full, and Programmable Almost Empty/Almost
CY7C42X5 have an output enable pin (OE). The read and write
Full status flags
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write
TTL compatible
applications. Clock frequencies up to 100 MHz are achievable.
Retransmit function
Retransmit and Synchronous Almost Full/Almost Empty flag
Output Enable (OE) pin features are available on these devices.
Depth expansion is possible using the cascade input (WXI, RXI),
Independent read and write enable pins
cascade output (WXO, RXO), and First Load (FL) pins. The
Center power and ground for reduced noise
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
Supports free running 50% duty cycle clock inputs
should be connected to the WXI and RXI pins of the first device.
Width Expansion Capability The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices should be tied to VCC.
Depth Expansion Capability
The CY7C42X5 provides five status pins. These pins are
Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and
decoded to determine one of five states: Empty, Almost Empty,
68-pin PLCC
Half Full, Almost Full, and Full (see Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the standalone and
width-expansion configurations. In the depth expansion, this pin
provides the expansion out (WXO) information that is used to
signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one clock
cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
VCC/SMODE is tied to VSS. All configurations are fabricated
using an advanced 0.65m N-Well CMOS technology. Input ESD
protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-45652 Rev. ** Revised May 02, 2008
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CY7C4425/4205/4215
CY7C4225/4235/4245
Logic Block Diagram
D
017
INPUT
REGISTER
WCLK WEN
FLAG
PROGRAM
WRITE
REGISTER
CONTROL
FF
RAM
EF
ARRAY
FLAG
64 x 18
PAE
LOGIC
256 x 18
PAF
512 x 18
SMODE
1K x 18
2K x 18
WRITE READ
4K x 18
POINTER POINTER
RS
RESET
LOGIC
FL/RT
TRISTATE
READ
WXI
OUTPUT REGISTER
EXPANSION
CONTROL
WXO/HF
LOGIC
RXI
OE
RXO
Q
017
RCLK REN
Pin Configuration
Figure 1. TQFP (Top View) Figure 2. PLCC (Top View)
98 7 6 54 3 2 1 68 67666564636261
D V /SMODE
10 60 CC
14
D
13 Q
11 59
14
D
12 Q
12 58 13
48 Q
D 1 14
15
D
Q 11 GND
13 57
D 2 47 13
14
D
GND 10 Q
D 3 46 14 56 12
13
Q CY7C4425
4 45 D
D 12 9 15 55 Q
12 11
Q
D 44 11 V
11 5 CY7C4205 V
CC 16 54
CY7C4425 CC
D 43 V
10 6 CC D
8 17 CY7C4215 53 Q
10
CY7C4205
D 42 Q
9 7 10
GND
Q
18 52 9
CY7C4225
CY7C4215
Q
D 41 9
8
8
D
7 GND
19 51
CY7C4235
D CY7C4225 GND
7 9 40
D
6 20 50 Q
8
10 39 Q
D CY7C4235 8 CY7C4245
6
D
5 49
21 Q
11 38 Q
D 7
5 7
CY7C4245
D
V
4 48
37 Q 22 CC
D 12 6
4
D
D 36
3 13 Q 3 23 47 Q
5 6
D 35 D
2 14 GND 2 Q
24 46 5
15 34 Q
D 4 D
1 1
25 45
GND
D 16 33 V
0 CC
D
0 26 44 Q
4
2728 2930 3132 33 34 35 36 37 38 3940 4142 43
Document Number: 001-45652 Rev. ** Page 2 of 22
[+] Feedback
17
64
PAE D
16
18
FL/RT 63 D
17
WCLK 19
62 GND
20
WEN 61
RCLK
21 60
WXI REN
V 22
CC 59 LD
23
58
PAF OE
24
57 RS
RXI
25 56 V
FF CC
26
55
WXO/HF GND
27
54
RXO EF
28
53 Q
17
Q
0
29
Q 52 Q
16
1
30
51 GND
GND
31
50 Q
Q 15
2
32
49
Q V /SMODE
3 CC
PAE D
15
D
FL/RT 16
D
WCLK 17
WEN GND
RCLK
WXI
V
CC REN
PAF LD
RXI OE
FF
RS
WXO/HF V
CC
RXO
GND
Q
0 EF
Q V
1 CC
Q
GND
17
Q
Q 16
2
GND
Q
3
Q
V 15
CC