CY7C421-20JXC Infineon

CY7C421512 9 Asynchronous FIFO CY7C421 512 9 Asynchronous FIFO 512 9 Asynchronous FIFO Features Functional Description Asynchronous First-In First-Out (FIFO) Buffer Memories The CY7C421 is a first-in first-out (FIFO) memory offered in 300-mil wide SOJ, TQFP & PLCC packages and it is 512 words 512 9 (CY7C421) by 9 bits wide. Each FIFO memory is organized such that the Dual-Ported RAM Cell data is read in the same sequential order that it was written. Full and empty flags are provided to prevent overflow and underflow. High Speed 50 MHz Read and Write Independent of Depth and Three additional pins are also provided to facilitate unlimited Width expansion in width, depth, or both. The depth expansion Low Operating Power: I = 35 mA technique steers the control signals from one device to another CC in parallel. This eliminates the serial addition of propagation Empty and Full Flags (Half Full Flag in Standalone) delays, so that throughput is not reduced. Data is steered in a similar manner. TTL Compatible The read and write operations may be asynchronous; each can Retransmit in Standalone occur at a rate of 50 MHz. The write operation occurs when the Expandable in Width write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high impedance state when R is PLCC, 7 7 TQFP, 300-Mil Molded SOJ HIGH. Pb-free Packages Available A Half Full (HF) output flag that is valid in the standalone and width expansion configurations is provided. In the depth Pin Compatible and Functionally Equivalent to IDT7201, and expansion configuration, this pin provides the expansion out AM7201 (XO) information that is used to tell the next FIFO that it is activated. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFO to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C421 is fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000 V and latch up is prevented by careful layout and guard rings. For a complete list of related documentation, click here. Selection Guide 512 9 -15 -20 Frequency (MHz) 40 33.3 Maximum Access Time (ns) 15 20 I (mA) 35 35 CC1 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06001 Rev. *J Revised November 27, 2014CY7C421 Logic Block Diagram DATA INPUTS (D D ) 0 8 WRITE W RAM ARRAY CONTROL 512x 9 WRITE READ POINTER POINTER THREE- STATE BUFFERS DATA OUTPUTS (Q Q ) 0 8 MR RESET LOGIC FL/RT READ R CONTROL FLAG EF LOGIC FF EXPANSION LOGIC XI XO/HF Document Number: 38-06001 Rev. *J Page 2 of 21