CY7C4425V /4205V/4215V CY7C4225V /4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
Features Functional Description
3.3V operation for low power consumption and easy The CY7C42X5V are high-speed, low-power, first-in first-out
integration into low-voltage systems (FIFO) memories with clocked read and write interfaces. All
are 18 bits wide. The CY7C42X5V can be cascaded to
High-speed, low-power, first-in first-out (FIFO)
increase FIFO depth. Programmable features include Almost
memories
Full/Almost Empty flags. These FIFOs provide solutions for a
64 x 18 (CY7C4425V)
wide variety of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, and communications
256 x 18 (CY7C4205V)
buffering.
512 x 18 (CY7C4215V)
These FIFOs have 18-bit input and output ports that are
1K x 18 (CY7C4225V)
controlled by separate clock and enable signals. The input port
2K x 18 (CY7C4235V) is controlled by a Free-Running Clock (WCLK) and a Write
Enable pin (WEN).
4K x 18 (CY7C4245V)
When WEN is asserted, data is written into the FIFO on the
0.65 CMOS
rising edge of the WCLK signal. While WEN is held active, data
High-speed 67-MHz operation (15-ns read/write cycle
is continually written into the FIFO on each cycle. The output
times)
port is controlled in a similar manner by a Free-Running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
Low power
CY7C42X5V have an Output Enable pin (OE). The read and
I = 30 mA
CC
write clocks may be tied together for single-clock operation or
5V tolerant inputs (V = 5V) the two clocks may be run independently for asynchronous
IH MAX
read/write applications. Clock frequencies up to 66 MHz are
Fully asynchronous and simultaneous read and write
achievable.
operation
Retransmit and Synchronous Almost Full/Almost Empty flag
Empty, Full, Half Full, and programmable Almost Empty
features are available on these devices.
and Almost Full status flags
Depth expansion is possible using the Cascade Input (WXI,
TTL-compatible
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins.
Retransmit function
The WXO and RXO pins are connected to the WXI and RXI
pins of the next device, and the WXO and RXO pins of the last
Output Enable (OE) pin
device should be connected to the WXI and RXI pins of the
Independent read and write enable pins
first device. The FL pin of the first device is tied to V and the
SS
Supports free-running 50% duty cycle clock inputs FL pin of all the remaining devices should be tied to V .
CC
Width-Expansion Capability The CY7C42X5V provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Depth-Expansion Capability
Half Full, Almost Full, and Full (see Table 2). The Half Full flag
64-pin 14 14 TQFP and 64-pin 10 10 STQFP
shares the WXO pin. This flag is valid in the stand-alone and
width-expansion configurations. In the depth expansion, this
Pb-Free packages available
pin provides the expansion out (WXO) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the write
clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. As mentioned previously, the
Almost Empty/Almost Full flags become synchronous if the
V /SMODE is tied to V . All configurations are fabricated
CC SS
using an advanced 0.65 P-Well CMOS technology. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-06029 Rev. *C Revised September 7, 2005CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
D
017
Logic Block Diagram
INPUT
REGISTER
WCLK WEN
FLAG
PROGRAM
WRITE
REGISTER
CONTROL
FF
RAM
EF
ARRAY
FLAG
64 x 18
PAE
LOGIC
256 x 18
PAF
512 x 18
SMODE
1K x 18
2K x 18
WRITE READ
4K x 18
POINTER POINTER
RS
RESET
LOGIC
FL/RT
THREESTATE
READ
WXI
OUTPUT REGISTER
EXPANSION
CONTROL
WXO/HF
LOGIC
RXI
OE
RXO
Q
017
RCLK REN
Pin Configuration
STQFP/TQFP
Top View
Q
D 1 48 14
15
Q
D 47 13
14 2
GND
D 3 46
13
Q
D 4 45 12
12
Q
D 44 11
5
11
CY7C4425V
V
D 6 43 CC
10
D CY7C4205V 42 Q
7 10
9
Q
D 41 9
8 8 CY7C4215V
D GND
7 9 40
CY7C4225V
39
D 10 Q
6 8
CY7C4235V
38
D 11 Q
5 7
CY7C4245V
D 12 37 Q
4 6
D 36
3 13 Q
5
D 14 35
2 GND
15 34 Q
D 4
1
D 33 V
16
0 CC
Document #: 38-06029 Rev. *C Page 2 of 20
17
PAE 64 D
16
18 D
FL/RT 63 17
19 GND
WCLK 62
20
WEN 61 RCLK
21
WXI 60 REN
22
V 59 LD
CC
PAF 23
58 OE
RXI 24 57 RS
25 V
FF 56 CC
26
WXO/HF 55 GND
27
RXO 54 EF
28
53 Q
Q 17
0
29
Q 52 Q
1 16
30
GND 51 GND
31
Q 50 Q
2
15
32
Q 49 V /SMODE
CC
3