3.3 VOLT CMOS SuperSync FIFO IDT72V255LA 8,192 x 18 16,384 x 18 IDT72V265LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Output enable puts data outputs into high impedance state FEATURES: Easily expandable in depth and width Choose among the following memory organizations: Independent Read and Write clocks (permit reading and IDT72V255LA 8,192 x 18 writing simultaneously) IDT72V265LA 16,384 x 18 Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- Pin-compatible with the IDT72V275/72V285 and IDT72V295/ pin Slim Thin Quad Flat Pack (STQFP) 72V2105 SuperSync FIFOs High-performance submicron CMOS technology Functionally compatible with the 5 Volt IDT72255/72265 family Industrial temperature range (40C to +85C) is available 10ns read/write cycle time (6.5ns access time) Green parts available, see ordering information Fixed, low first word data latency time 5V input tolerant Auto power down minimizes standby power consumption DESCRIPTION: Master Reset clears entire FIFO The IDT72V255LA/72V265LA are functionally compatible versions of the Partial Reset clears data, but retains programmable settings IDT72255/72265 designed to run off a 3.3V supply for very low power Retransmit operation with fixed, low first word data consumption. The IDT72V255LA/72V265LA are exceptionally deep, high latency time speed, CMOS First-In-First-Out (FIFO) memories with clocked read and Empty, Full and Half-Full flags signal FIFO status write controls. These FIFOs offer numerous improvements over previous Programmable Almost-Empty and Almost-Full flags, each flag SuperSync FIFOs, including the following: can default to one of two preselected offsets The limitation of the frequency of one clock input with respect to the other Program partial flags by either serial or parallel means has been removed. The Frequency Select pin (FS) has been removed, Select IDT Standard timing (using EF and FF flags) or First thus it is no longer necessary to select which of the two clock inputs, RCLK Word Fall Through timing (using OR and IR flags) or WCLK, is running at the higher frequency. FUNCTIONAL BLOCK DIAGRAM D0 -D17 WEN WCLK LD SEN INPUT REGISTER OFFSET REGISTER FF/IR PAF FLAG EF/OR WRITE CONTROL LOGIC PAE LOGIC HF FWFT/SI RAM ARRAY 8,192 x 18 WRITE POINTER 16,384 x 18 READ POINTER READ CONTROL RT LOGIC OUTPUT REGISTER MRS RESET RCLK LOGIC PRS REN 4672 drw 01 Q0 -Q17 OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES JANUARY 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4672/5IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO COMMERCIAL AND INDUSTRIAL 8,192 x 18, 16,384 x 18 TEMPERATURE RANGES The input port is controlled by a Write Clock (WCLK) input and a Write Enable DESCRIPTION (CONTINUED) (WEN) input. Data is written into the FIFO on every rising edge of WCLK when The period required by the retransmit operation is now fixed and short. WEN is asserted. The output port is controlled by a Read Clock (RCLK) input The first word data latency period, from the time the first word is written to and Read Enable (REN) input. Data is read from the FIFO on every rising an empty FIFO to the time it can be read, is now fixed and short. (The variable edge of RCLK when REN is asserted. An Output Enable (OE) input is provided clock cycle counting delay associated with the latency period found on for three-state control of the outputs. previous SuperSync devices has been eliminated on this SuperSync The frequencies of both the RCLK and the WCLK signals may vary from 0 family.) to fMAX with complete independence. There are no restrictions on the SuperSync FIFOs are particularly appropriate for networking, video, frequency of one clock input with respect to the other. telecommunications, data communications and other applications that need to buffer large amounts of data. PIN CONFIGURATIONS PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 WEN 1 48 Q17 SEN 2 47 Q16 (1) DC 3 46 GND VCC 4 45 Q15 GND 5 44 Q14 D17 6 43 VCC 7 42 D16 Q13 D15 8 41 Q12 9 40 D14 Q11 D13 10 39 GND 11 38 D12 Q10 12 37 D11 Q9 13 36 D10 Q8 14 35 D9 Q7 15 34 D8 Q6 16 33 D7 GND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4672 drw 02 TQFP (PN64, ORDER CODE: PF) STQFP (PP64, ORDER CODE: TF) TOP VIEW NOTE: 1. DC = Dont Care. Must be tied to GND or VCC, cannot be left open. 2 WCLK PRS D5 MRS D4 D3 LD D2 FWFT/SI GND D1 D0 FF/IR GND PAF Q0 HF Q1 VCC PAE GND EF/OR Q2 Q3 RCLK VCC REN RT Q4 Q5 OE D6