TM 3.3 VOLT CMOS SyncFIFO 72V3611 64 x 36 Available in space-saving 120-pin Thin Quad Flatpack (PFG) FEATURES: Green parts available, see ordering information 64 x 36 storage capacity Supports clock frequencies up to 67MHz Fast access times of 10ns DESCRIPTION: Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of The IDT72V3611 is designed to run off a 3.3V supply for exceptionally low data on a single clock edge) power consumption. This device is a monolithic, high-speed, low-power, Synchronous data buffering from Port A to Port B CMOS Synchronous (clocked) FIFO memory which supports clock frequen- Mailbox bypass register in each direction cies up to 67MHz and has read access times as fast as 10ns. The 64 x 36 dual- Programmable Almost-Full (AF) and Almost-Empty (AE) flags port FIFO buffers data from Port A to Port B. The FIFO operates in IDT Standard Microprocessor Interface Control Logic mode and has flags to indicate empty and full conditions, and two programmable Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected Empty Flag (EF) and Almost-Empty (AE) flags synchronized by number of words is stored in memory. Communication between each port can CLKB take place through two 36-bit mailbox registers. Each mailbox register has a Passive parity checking on each Port flag to signal when new mail has been stored. Parity is checked passively on Parity Generation can be selected for each Port each port and may be ignored if not desired. Parity generation can be selected FUNCTIONAL BLOCK DIAGRAM CLKA CSA Port-A W/RA Control Logic ENA MBA MBF1 PEFB Parity Gen/Check Mail 1 Register RST PGB Reset Logic ODD/ EVEN RAM ARRAY 64 x 36 36 36 A0 - A35 Read Write B0 - B35 Pointer Pointer FF Status Flag EF AF Logic AE FIFO Programmable FS0 Flag Offset FS1 Registers PGA Mail 2 Register Parity CLKB Gen/Check CSB Port-B PEFA W/RB Control MBF2 ENB Logic MBB 4657 drw01 COMMERCIAL TEMPERATURE RANGE 1 Feb.10.20 Input Register Parity Generation Output RegisterTM 72V3611 3.3V, CMOS SyncFIFO 64 x 36 COMMERCIAL TEMPERATURE RANGE bidirectional interface between microprocessors and/or buses with synchro- DESCRIPTION (CONTINUED) nous control. for data read from each port. Two or more devices may be used in parallel to The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage create wider data paths. synchronized to the port clock that writes data into its array (CLKA). The Empty The IDT72V3611 is a synchronous (clocked) FIFO, meaning each port Flag (EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized employs a synchronous interface. All data transfers through a port are gated to the port clock that reads data from its array. to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for The IDT72V3611 is characterized for operation from 0C to 70C. This each port are independent of one another and can be asynchronous or device is fabricated using high speed, submicron CMOS technology. coincident. The enables for each port are arranged to provide a simple PIN CONFIGURATION NC 60 B23 91 CSB 59 B24 92 ENB 58 B25 93 57 CLKB B26 94 56 W/RB VCC 95 55 VCC B27 96 PGB B28 54 97 PEFB 53 B29 98 MBF1 52 GND 99 51 MBB B30 100 50 NC B31 101 NC 49 B32 102 48 NC B33 103 47 NC B34 104 GND 46 B35 105 RST 45 GND 106 44 ODD/EVEN A35 107 72V3611 FS0 43 A34 108 42 FS1 A33 109 41 MBA A32 110 MBF2 40 A31 111 PEFA 39 A30 112 PGA 38 GND 113 37 VCC A29 114 W/RA 36 A28 115 35 CLKA A27 116 34 ENA VCC 117 33 CSA A26 118 FF 32 A25 119 31 AF A24 120 4657 drw02 NOTES: 1. Pin 1 identifier in corner. 2. NC = No internal connection TQFP (PNG120, order code: PFG) TOP VIEW 2 Feb.10.20 A23 1 B22 90 A22 2 B21 89 A21 3 GND 88 GND 4 B20 87 A20 5 B19 86 A19 6 85 B18 A18 7 84 B17 A17 8 83 B16 A16 9 82 B15 A15 10 81 B14 A14 11 80 B13 A13 12 79 B12 A12 13 B11 78 A11 14 77 B10 A10 15 76 GND GND 16 75 B9 A9 17 74 B8 A8 18 73 B7 A7 19 72 VCC VCC 20 71 B6 A6 21 70 B5 A5 22 69 B4 A4 23 68 B3 A3 24 67 GND GND 25 66 B2 A2 26 65 B1 A1 27 64 B0 A0 28 63 EF NC 29 AE 62 NC 30 NC 61