IDT74ALVC162334 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74ALVC162334 UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS DESCRIPTION: FEATURES: This 16-bit universal bus driver is built using advanced dual metal CMOS 0.5 MICRON CMOS Technology technology. Data flow from A to Y is controlled by the output-enable (OE) Typical tSK(o) (Output Skew) < 250ps input. The device operates in the transparent mode when the latch-enable ESD > 2000V per MIL-STD-883, Method 3015 > 200V using (LE) input is low. When LE is high, the A data is latched if the clock (CLK) machine model (C = 200pF, R = 0) input is held at a high or low logic level. If LE is high, the A data is stored VCC = 3.3V 0.3V, Normal Range in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, VCC = 2.7V to 3.6V, Extended Range the outputs are in the high-impedance state. VCC = 2.5V 0.2V The ALVC162334 has series resistors in the device output structure CMOS power levels (0.4 W typ. static) which will significantly reduce line noise when used with light loads. This Rail-to-Rail output swing for increased noise margin driver has been designed to drive 12mA at the designated threshold Available in TSSOP package levels. DRIVE FEATURES: APPLICATIONS: Balanced Output Drivers: 12mA SDRAM Modules Low Switching Noise PC Motherboards Workstations FUNCTIONAL BLOCK DIAGRAM 1 OE 48 CLK 25 LE 47 A1 1D 2 Y1 C1 CLK TO 15 OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JUNE 2016 1 2016 Integrated Device Technology, Inc. DSC-4687/7IDT74ALVC162334 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V OE 1 (3) 48 CLK VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V Y1 2 TSTG Storage Temperature 65 to +150 C 47 A1 IOUT DC Output Current 50 to +50 mA Y2 3 A2 46 IIK Continuous Clamp Current, 50 mA GND 4 VI < 0 or VI > VCC GND 45 IOK Continuous Clamp Current, VO < 0 50 mA Y3 5 44 A3 ICC Continuous Current through each 100 mA 6 Y4 ISS VCC or GND 43 A4 NOTES: VCC 7 42 VCC 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation Y5 8 41 A5 of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating Y6 9 A6 40 conditions for extended periods may affect reliability. 2. VCC terminals. GND 10 39 GND 3. All terminals except VCC. Y7 11 A7 38 CAPACITANCE (TA = +25C, F = 1.0MHz) Y8 12 A8 37 (1) Symbol Parameter Conditions Typ. Max. Unit Y9 13 A9 36 CIN Input Capacitance VIN = 0V 5 7 pF 14 Y10 35 A10 COUT Output Capacitance VOUT = 0V 7 9 pF GND 15 34 GND COUT I/O Port Capacitance VIN = 0V 7 9 pF NOTE: Y11 16 A11 33 1. As applicable to the device type. Y12 17 A12 32 VCC 18 VCC 31 Y13 19 30 A13 (1) Y14 FUNCTION TABLE 20 A14 29 Inputs Outputs GND 21 28 GND OE LE CLK Ax Yx Y15 22 27 A15 HX X X Z Y16 23 26 A16 LL X L L NC 24 LL X H H LE 25 LH LL LH HH TSSOP (2) L H L or H X Y TOP VIEW 0 NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level PIN DESCRIPTION X = Dont Care Z = High Impedance Pin Names Description = LOW-to-HIGH transition OE 3-State Output Enable Inputs (Active LOW) 2. Output level before the indicated steady-state input conditions were established. CLK Register Input Clock LE Latch Enable (Active LOW) A x Data Inputs Y x 3-State Outputs 2