IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74FCT163373A/C TRANSPARENT LATCH FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT163373 16-bit transparent D-type latches are built using Typical tSK(o) (Output Skew) < 250ps advanced dual metal CMOS technology. These high-speed, low-power ESD > 2000V per MIL-STD-883, Method 3015 > 200V using latches are ideal for temporary storage of data. They can be used for machine model (C = 200pF, R = 0) implementing memory address latches, I/O ports, and bus drivers. The VCC = 3.3V 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Output Enable and Latch Enable controls are organized to operate each Range device as two 8-bit latches or one 16-bit latch. Flow-through organization CMOS power levels (0.4 W typ. static) of signal pins simplifies layout. All inputs are designed with hysteresis for Rail-to-rail output swing for increased noise margin improved noise margin. Low Ground Bounce (0.3V typ.) The inputs of FCT163373 can be driven from either 3.3V or 5V devices. Inputs (except I/O) can be driven by 3.3V or 5V components This feature allows the use of these transparent latches as translators in a Available in SSOP and TSSOP packages mixed 3.3V/5V supply system. With xLE inputs high, the FCT163373 can be used as a buffer to connect 5V components to a 3.3V bus. FUNCTIONAL BLOCK DIAGRAM 1 24 2OE 1OE 48 25 2LE 1LE 47 36 D 1D1 D 2D1 2 13 1O1 2O1 C C TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2009 1 2009 Integrated Device Technology, Inc. DSC-5416/6IDT74FCT163373A/C 3.3V CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V (3) 1 48 VTERM Terminal Voltage with Respect to GND 0.5 to 7 V 1LE 1OE (4) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 2 47 1O1 1D1 TSTG Storage Temperature 65 to +150 C 3 46 1O2 1D2 IOUT DC Output Current 60 to +60 mA GND 4 45 GND NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 5 44 1O3 1D3 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational 6 43 sections of this specification is not implied. Exposure to absolute maximum rating 1O4 1D4 conditions for extended periods may affect reliability. VCC 7 42 VCC 2. Vcc terminals. 3. Input terminals. 8 41 4. Outputs and I/O terminals. 1O5 1D5 9 40 1O6 1D6 GND 10 39 GND CAPACITANCE (TA = +25C, F = 1.0MHz) 11 38 1O7 1D7 (1) Symbol Parameter Conditions Typ. Max. Unit 12 37 1O8 1D8 CIN Input Capacitance VIN = 0V 3.5 6 pF 13 36 2O1 2D1 COUT Output Capacitance VOUT = 0V 3.5 8 pF NOTE: 14 35 2O2 2D2 1. This parameter is measured at characterization but not tested. GND 15 34 GND 16 33 2O3 2D3 PIN DESCRIPTION 17 32 2O4 2D4 Pin Names Description VCC 18 31 VCC x D x Data Inputs 19 30 xLE Latch Enable Input (Active HIGH) 2O5 2D5 xOE Output Enable Input (Active LOW) 20 29 2O6 2D6 x O x 3-State Outputs GND 21 28 GND 22 27 2O7 2D7 23 26 2O8 2D8 24 25 2LE (1) 2OE FUNCTION TABLE Inputs Outputs SSOP/ TSSOP xDx xLE xOE xBx TOP VIEW HHL H LH L L (2) XL L O XX H Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2