74FCT3244QG8 Renesas

74FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS OCTAL 74FCT3244/A BUFFER/LINE DRIVER DESCRIPTION: FEATURES: 0.5 MICRON CMOS Technology The FCT3244/A octal buffer/line drivers are built using advanced dual ESD > 2000V per MIL-STD-883, Method 3015 > 200V using metal CMOS technology. These high-speed, low-power buffers are machine model (C = 200pF, R = 0) designed to be used as memory data and address drivers, clock drivers, VCC = 3.3V 0.3V, Normal Range and bus-oriented transmitter/receivers. The three-state controls are VCC = 2.7V to 3.6V, Extended Range designed to operate these devices in a dual-nibble or single-byte mode. All CMOS power levels (0.4W typ. static) inputs are designed with hysteresis for improved noise margin. Rail-to-Rail output swing for increased noise margin Available in QSOP, SOIC, SSOP, and TSSOP packages FUNCTIONAL BLOCK DIAGRAM 1 1OE 2 18 1A1 1Y1 4 16 1A2 1Y2 14 6 1A3 1Y3 8 12 1A4 1Y4 19 2OE 11 9 2A1 2Y1 13 7 2A2 2Y2 5 15 2A3 2Y3 17 3 2A4 2Y4 INDUSTRIAL TEMPERATURE RANGE 1 Feb.11.2074FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE (1) ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V (3) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V Vcc 1OE 1 (4) 20 VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 1A 1 2 19 2OE TSTG Storage Temperature 65 to +150 C Y 2 4 IOUT DC Output Current 60 to +60 mA 3 18 1Y1 NOTES: 1A2 2A4 4 17 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may 2Y3 1Y2 cause permanent damage to the device. This is a stress rating only and functional 5 16 operation of the device at these or any other conditions above those indicated in 1A3 2A 3 6 15 the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 2 Y 1Y 3 7 14 2. VCC terminals. 1A 4 2A 2 8 13 3. Input terminals. 2Y 1 4. Outputs and I/O terminals. 1Y4 9 12 GND 1 2A 10 11 TOP VIEW CAPACITANCE (TA = +25C, F = 1.0MHz) (1) Symbol Parameter Conditions Typ. Max. Unit Package Type Package Code Order Code CIN Input Capacitance VIN = 0V 3.5 6 pF QSOP PCG20 QG COUT Output Capacitance VOUT = 0V 4 8 pF SOIC PSG20 SOG NOTE: 1. This parameter is measured at characterization but not tested. TSSOP PGG20 PGG SSOP PYG20 PYG PIN DESCRIPTION Pin Names Description xOE 3State Output Enable Inputs (Active LOW) x A x Data Inputs x Y x 3-State Outputs (1) FUNCTION TABLE Inputs Outputs xOE xAx xYx LL L LH H HX Z NOTE: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High Impedance 2 Feb.11.20