Low Skew 1 to 4 Clock Buffer 74FCT38074S DATASHEET Description Features The 74FCT38074S is a low skew, single input to four output, Low additive phase jitter RMS: 50fs clock buffer. The 74FCT38074S has best in class additive Extremely low skew outputs (50ps) phase Jitter of sub 50 fsec. Low cost clock buffer IDT makes many non-PLL and PLL based low skew output Packaged in 8-pin SOIC and 8-pin DFN, Pb-free devices as well as Zero Delay Buffers to synchronize clocks. Input/Output clock frequency up to 200 MHz Contact us for all of your clocking needs. Low power CMOS technology Operating voltages of 1.8V to 3.3V Extended temperature range (-40 to +105C) Block Diagram Q1 Q2 ICLK Q3 Q4 74FCT38074S REVISION A 03/18/15 1 2015 Integrated Device Technology, Inc.74FCT38074S DATASHEET Pin Assignments VDD 1 8 Q4 VDD 1 8 Q4 VDD 2 7 Q3 VDD 2 7 Q3 ICLK 3 6 Q2 ICLK 3 6 Q2 GND 4 5 Q1 GND 4 5 Q1 8-pin SOIC 8-pin DFN Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. 2 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. 3 ICLK Input Clock input. 4 GND Power Connect to ground. 5 Q1 Output Clock output 1. 6 Q2 Output Clock Output 2. 7 Q3 Output Clock Output 3. 8 Q4 Output Clock Output 4. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be connected between VDD on pins 1 and 2, and GND on pin 4, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the 74FCT38074S is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15 ps of skew. LOW SKEW 1 TO 4 CLOCK BUFFER 2 REVISION A 03/18/15