74FCT38075SCMGI Renesas

Low Skew 1 to 5 Clock Buffer 74FCT38075S DATASHEET Description Features The 74FCT38075S is a low skew, single input to five output, Extremely low RMS Additive Phase Jitter: 50fs clock buffer. The 74FCT38075S has best in class additive Low output skew: 50ps phase Jitter of sub 50 fsec. Packaged in 8-pin SOIC and 8-pin DFN IDT makes many non-PLL and PLL based low output skew Pb (lead) free package devices as well as Zero Delay Buffers to synchronize clocks. Low power CMOS technology Contact us for all of your clocking needs. Operating voltages of 1.8V to 3.3V Extended temperature range (-40C to +105C) Block Diagram Q0 Q1 ICLK Q2 Q3 Q4 74FCT38075S REVISION A 03/18/15 1 2015 Integrated Device Technology, Inc.74FCT38075S DATASHEET Pin Assignments 1 8 Q4 Q3 Q4 1 8 Q3 2 7 VDD Q2 VDD 2 7 Q2 3 6 ICLK Q1 ICLK 3 6 Q1 GND 4 5 Q0 GND 4 5 Q0 8-pin DFN 8-pin SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 Q4 Output Clock Output 4. 2 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. 3 ICLK Input Clock input. 4 GND Power Connect to ground. 5 Q0 Output Clock output 0. 6 Q1 Output Clock output 1. 7 Q2 Output Clock Output 2. 8 Q3 Output Clock Output 3. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be connected between VDD on pin 2 and GND on pin 4, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the 74FCT38075S is capable of, careful attention must be paid to board layout. Essentially, all five outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15 ps of skew. LOW SKEW 1 TO 5 CLOCK BUFFER 2 REVISION A 03/18/15