Data Sheet HD74LV1G126A R04DS0026EJ0800 Rev.8.00 Bus Buffer Gate with 3state Output Jan 10, 2014 Description The HD74LV1G126A has a bus buffer gate with 3state output in a 5 pin package. Output is disabled when the associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE should be connected to V through a pull-down resistor the minimum value of the resistor is determined by the current CC sourcing capability of the driver. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features The basic gate function is lined up as Renesas uni logic series. Supplied on emboss taping for high-speed automatic mounting. Electrical characteristics equivalent to the HD74LV126A Supply voltage range : 1.65 to 5.5 V Operating temperature range : 40 to +85C All inputs V (Max.) = 5.5 V ( V = 0 V to 5.5 V) IH CC All outputs V (Max.) = 5.5 V ( V = 0 V, Output : Z) O CC Output current 6 mA ( V = 3.0 V to 3.6 V), 12 mA ( V = 4.5 V to 5.5 V) CC CC All the logical input has hysteresis voltage for the slow transition. Ordering Information Package Code Package Taping Abbreviation Part Name Package Type (Previous Code) Abbreviation (Quantity) PTSP0005ZC-A HD74LV1G126ACME CMPAK5 pin CM E (3000 pcs/reel) (CMPAK-5V) PUSN0005KA-A HD74LV1G126AVSE VSON5 pin VS E (3000 pcs/reel) (TNP-5DV) Note: Please consult the sales office for the above package availability. Outline and Article Indication HD74LV1G126A Index band Marking L C = Control code CMPAK5 R04DS0026EJ0800 Rev.8.00 Page 1 of 8 Jan 10, 2014 HD74LV1G126A Outline and Article Indication HD74LV1G126A Marking L C = Control code VSON5 Function Table Inputs Output Y OE A H H H H L L L X Z H : High level L : Low level X : Immaterial Z : High impedance Pin Arrangement 1 OE 5 V CC A 2 GND 3 4 Y (Top view) R04DS0026EJ0800 Rev.8.00 Page 2 of 8 Jan 10, 2014