IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE OBSOLETE PART LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16373A 16-bit transparent D-type latch is built using advanced Typical tSK(o) (Output Skew) < 250ps dual metal CMOS technology. This high-speed, low-power latch is ideal ESD > 2000V per MIL-STD-883, Method 3015 > 200V using for temporary storage of data. The LVCH16373A can be used for machine model (C = 200pF, R = 0) implementing memory address latches, I/O ports, and bus drivers. The VCC = 3.3V 0.3V, Normal Range Output Enable and Latch Enable controls are organized to operate each VCC = 2.7V to 3.6V, Extended Range device as two 8-bit latches or one 16-bit latch. Flow-through organization CMOS power levels (0.4 W typ. static) of signal pins simplifies layout. All inputs are designed with hysteresis for All inputs, outputs, and I/O are 5V tolerant improved noise margin. Supports hot insertion All pins of the LVCH16373A can be driven from either 3.3V or 5V devices. Available in TSSOP package This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. DRIVE FEATURES: The LVCH16373A has bus-hold which retains the inputs last state High Output Drivers: 24mA whenever the input goes to a high impedance. This prevents floating inputs Reduced system switching noise and eliminates the need for pull-up/down resistors. APPLICATIONS: 5V and 3.3V mixed voltage systems Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1 24 2OE 1OE 25 48 1LE 2LE 47 36 D D 1D1 2D1 13 2 C Q 2Q1 C Q 1Q1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS INDUSTRIAL TEMPERATURE RANGE MARCH 2006 1 2006 Integrated Device Technology, Inc. DSC-4735/6 OBSOLETE PART NOT RECOMMENDED FOR NEW DESIGNSIDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND 0.5 to +6.5 V 1LE 1 48 1OE TSTG Storage Temperature 65 to +150 C 2 1D1 1Q1 47 IOUT DC Output Current 50 to +50 mA IIK Continuous Clamp Current, 50 mA 1D2 1Q2 3 46 IOK VI < 0 or VO < 0 GND 4 45 GND ICC Continuous Current through each 100 mA ISS VCC or GND 5 1D3 44 1Q3 NOTE: 6 1D4 1Q4 43 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation VCC 7 VCC 42 of the device at these or any other conditions above those indicated in the operational 8 1D5 sections of this specification is not implied. Exposure to absolute maximum rating 1Q5 41 conditions for extended periods may affect reliability. 1D6 9 40 1Q6 10 GND GND 39 11 1D7 38 1Q7 CAPACITANCE (TA = +25C, F = 1.0MHz) 12 1D8 1Q8 37 (1) Symbol Parameter Conditions Typ. Max. Unit 13 2D1 2Q1 36 CIN Input Capacitance VIN = 0V 4.5 6 pF 2D2 14 2Q2 35 COUT Output Capacitance VOUT = 0V 6.5 8 pF 15 GND GND 34 CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 16 NOTE: 33 2Q3 2D3 1. As applicable to the device type. 17 32 2D4 2Q4 18 31 VCC VCC 19 30 2D5 2Q5 PIN DESCRIPTION 20 29 2D6 2Q6 Pin Names Description 21 GND GND 28 (1) xDx Data Inputs 22 27 2D7 2Q7 xLE Latch Enable Input 23 xOE Output Enable Inputs (Active LOW) 2D8 2Q8 26 x Q x 3-State Outputs 24 2LE 2OE 25 NOTE: 1. These pins haveBus-Hol. All other pins are standard inputs, outputs, or I/Os. TSSOP TOP VIEW (1) FUNCTION TABLE Inputs Outputs xDx xLE xOE xQx HH L H LH L L (2) XL L Q XX H Z NOTES: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2