1-to-1 Differential-to-LVCMOS/LVTTL 83021I Translator Datasheet General Description Features The 83021I is a 1-to-1 Differential-to-LVCMOS/ LVTTL Translator One LVCMOS/LVTTL output and a member of the family of High Performance Clock Solutions Differential CLK/nCLK input pair from IDT. The differential input is highly flexible and can accept the CLK/nCLK pair can accept the following differential following input types: LVPECL, LVDS, LVHSTL, SSTL, and HCSL. input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL The small 8-lead SOIC footprint makes this device ideal for use in Output frequency: 350MHz (typical) applications with limited board space. Part-to-part skew: 500ps (maximum) Additive phase jitter, RMS: 0.21ps (typical), 3.3V output Full 3.3V and 2.5V operating supply -40C to 85C ambient operating temperature Pin Assignment Block Diagram Pulldown CLK VDD nc 1 8 Q0 Pullup CLK 2 7 Q0 nCLK nCLK 3 6 nc GND nc 4 5 83021I 8-Lead SOIC, 150Mil 3.9mm x 4.9mm x 1.375mm package body M Package Top View 2015 Integrated Device Technology, Inc 1 December 14, 201583021I Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 4, 6 nc Unused No connect. 2 CLK Input Pulldown Non-inverting differential clock input. 3 nCLK Input Pullup Inverting differential clock input. 5 GND Power Power supply ground. 7 Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 8V Power Positive supply pin. DD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN C Power Dissipation Capacitance V = 3.6V 23 pF PD DD R Output Impedance 5 7 12 OUT 2015 Integrated Device Technology, Inc 2 December 14, 2015