Low Skew, 1-to-2 LVCMOS / LVTTL 8302I-01 Datasheet Fanout Buffer W/ Complementary Output FEATURES DESCRIPTION Complementary LVCMOS / LVTTL output The 8302I-01 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout Buffer w/Complementary Output. The 8302I-01 has a single ended clock LVCMOS / LVTTL clock input accepts LVCMOS or input. The single ended clock input accepts LVCMOS or LVTTL input LVTTL input levels levels. The 8302I-01 is characterized at full 3.3V for input V , and DD mixed 3.3V and 2.5V for output operating supply modes (V ). Maximum output frequency: 250MHz DDO Guaranteed output and part-to-part skew characteristics make the Output skew: 165ps (maximum) 8302I-01 ideal for clock distribution applications demanding well de ned performance and repeatability. Part-to-part skew: 800ps (maximum) Small 8 lead SOIC package saves board space Full 3.3V or 3.3V core/2.5V output supply modes -40C to 85C ambient operating temperature Available in lead-free compliant package BLOCK DIAGRAM PIN ASSIGNMENTS VDDO 1 8 Q Q VDD 2 7 GND CLK 3 6 VDDO CLK nQ GND 4 5 nQ 8302I-01 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 1 May 4, 20178302I-01 Datasheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 6 V Power Output supply pins. DDO 2V Power Power supply pin. DD 3 CLK Input Pulldown LVCMOS / LVTTL clock input. 4,7 GND Power Power supply ground. 5 nQ Output Complementary clock output. LVCMOS / LVTTL interface levels. 8 Q Output Clock output. LVCMOS / LVTTL interface levels. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN V , V = 3.465V 22 pF Power Dissipation Capacitance DD DDO C PD (per output) V = 3.465V, V = 2.625V 16 pF DD DDO R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance 5 7 12 OUT 2 May 4, 2017