LOW SKEW, 1-TO-2 8302I Data Sheet LVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The 8302I is a low skew, 1-to-2 LVCMOS Fanout Buffer. The 2 LVCMOS / LVTTL outputs 8302I has a single ended clock input. The single ended clock LVCMOS / LVTTL clock input accepts LVCMOS input accepts LVCMOS or LVTTL input levels. The 8302I features or LVTTL input levels a pair of LVCMOS outputs. The 8302I is characterized at full 3.3V for input V , and mixed 3.3V and 2.5V for output operating Maximum output frequency: 200MHz DD supply modes (V ). Guaranteedoutput and part-to-part skew DDO Output skew: 40ps (typical) characteristics make the 8302I ideal for clock distribution applications demanding well de ned performance Part-to-part skew: 250ps (typical) and repeatibility. Small 8 lead SOIC package saves board space Full 3.3V or 3.3V core, 2.5V supply modes -40C to 85C ambient operating temperature Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT VDDO Q0 1 8 VDD 2 7 GND VDDO CLK 3 6 Q0 Q1 GND 4 5 CLK Q1 8302I 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 2016 Integrated Device Technology, Inc 1 Revision A March 4, 20168302I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 6 V Power Output supply pins. DDO 2V Power Core supply pin. DD 3 CLK Input Pulldown LVCMOS / LVTTL clock input. 4,7 GND Power Power supply ground. 5 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 8 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN V , V = 3.465V 22 pF Power Dissipation Capacitance DD DDO C PD (per output) V = 3.465V, V = 2.625V 16 pF DD DDO R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance 7 OUT 2016 Integrated Device Technology, Inc 2 Revision A March 4, 2016