Low Skew, 1-to-4 LVCMOS/LVTTL 8304I Data Sheet Fanout Buffer GENERAL DESCRIPTION FEATURES The 8304I is a low skew, 1-to-4 Fanout Buffer. The 8304I is charac- Four LVCMOS / LVTTL outputs terized at full 3.3V for input V , and mixed 3.3V and 2.5V for output DD LVCMOS clock input operating supply modes (V ). Guaranteed output and part-to-part DDO skew characteristics make the 8304I ideal for those clock distribution CLK can accept the following input levels: LVCMOS, LVTTL applications demanding well de ned performance and repeatability. Maximum output frequency: 166MHz Output skew: 60ps (maximum) Part-to-part skew: 650ps (maximum) Small 8 lead SOIC package saves board space 3.3V input, outputs may be either 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) compliant package BLOCK DIAGRAM PIN ASSIGNMENT Q0 VDDO Q3 1 8 VDD 2 7 Q2 Q1 CLK 3 6 Q1 GND 4 5 Q0 Pulldown CLK Q2 8304I 8-Lead SOIC Q3 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 2015 Integrated Device Technology, Inc 1 December 10, 20158304I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Output supply pin. Connect to 3.3V or 2.5V. DDO 2V Power Positive supply pin. Connect to 3.3V. DD 3 CLK Input Pulldown LVCMOS / LVTTL clock input. 4 GND Power Power supply ground. Connect to ground. 5 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. 6 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 7 Q2 Output Single clock output. LVCMOS / LVTTL interface levels. 8 Q3 Output Single clock output. LVCMOS / LVTTL interface levels. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN Power Dissipation Capacitance C 15 pF V , V = 3.465V PD (per output) DD DDO R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance 7 OUT 2015 Integrated Device Technology, Inc 2 December 10, 2015