Low Skew, PCI-X 1-to-4 Fanout Buffer 830584I Datasheet GENERAL DESCRIPTION FEATURES The 830584I is a low skew, general purpose PCI-X 1-to-4 Fanout General purpose and PCI-X 1:4 clock buffer Buffer and a member of the family of High Performance Clock Solutions Four single-ended LVCMOS/LVTTL clock outputs from IDT. Guaranteed output and part-to-part skew characteristics make the 830584I ideal for those clock distribution applications One single-ended LVCMOS/LVTTL clock input demanding well de ned performance and repeatablility. The 830584I Maximum output frequency: 140MHz is designed and characterized from -40C to 85C for industrial applications and is packaged in an 8 TSSOP package. Output enable control (outputs disabled in logic low state) Output skew: 100ps (maximum) Part-to-part skew: 400ps (maximum) Additive phase jitter, RMS: 0.15ps (typical) Space-saving 8 lead TSSOP package Full 3.3V operating supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT CLKIN Q3 1 8 Q0 OE Q2 2 7 Q0 VDD 3 6 GND 4 5 Q1 Q1 CLKIN 830584I Q2 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body Q3 G Package OE Top View 2015 Integrated Device Technology, Inc 1 December 16, 2015830584I Datasheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description Single-ended clock input reference signal. 1 CLKIN Input LVCMOS/LVTTL interface levels. Output enable control input pin. See Table 3, Function Table. 2 OE Input LVCMOS / LVTTL interface levels. 3, 5, 7. 8 Q0, Q1, Q2, Q3 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 4 GND Power Power supply ground. 6V Power Positive supply pin. DD TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Output Impedance 15 OUT TABLE 3. FUNCTION TABLE Inputs Outputs OE CLKIN Q0:Q3 00 0 01 0 10 0 11 1 2015 Integrated Device Technology, Inc 2 December 16, 2015