Low Skew, 1-TO-16 LVCMOS/LVTTL 83115 Fanout Buffer DATA SHEET General Description Features The 83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer Sixteen LVCMOS / LVTTL outputs, 15 output impedance from IDT. The 83115 single-ended clock input accepts LVCMOS or One LVCMOS / LVTTL clock input LVTTL input levels. The 83115 operates at full 3.3V supply mode Maximum output frequency: 200MHz over the commercial temperature range. Guaranteed output and All inputs are 5V tolerant part-to-part skew characteristics make the 83115 ideal for those clock distribution applications demanding well defined Output skew: 250ps (maximum) performance and repeatability. Part-to-part skew: 800ps (maximum) Additive phase jitter, RMS: 0.09ps (typical) Full 3.3V operating supply 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment OE2 VDD OE2 OE1 1 28 4 2 27 Q15 Q0 3 26 Q14 Q1 Q2 Q13 4 25 IN VDD 5 24 VDD VDD 6 23 VDD Q3 7 22 Q12 Q0 Q15 Q4 8 21 Q11 Q14 Q1 GND GND 9 20 10 19 GND GND Q13 Q2 Q5 11 18 Q10 Q3 Q12 Q6 12 17 Q9 Q7 13 16 Q8 Q4 Q11 OE0 IN 14 15 Q5 Q10 83115 Q6 Q9 Q8 28-Lead SSOP, 150mil Q7 9.9mm x 3.9mm x 1.5mm package body 4 R Package OE1 GND OE0 Top View 83115 Rev C 3/20/15 1 2015 Integrated Device Technology, Inc. OE1 OE2 OE0 OE283115 DATA SHEET Table 1. Pin Descriptions Number Name Type Description Output enable pin. When LOW, forces outputs Q 2:7 to Hi-Z state. 1 OE1 Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. See Table 3. 2, 3, 4, 7, 8, Q0, Q1, Q2, Q3, 11, 12, 13, Q4, Q5, Q6, Single-ended clock outputs. 15 output impedance. 16, 17, 18, Q7, Q8, Q9, Output LVCMOS/LVTTL interface levels. 21, 22, 25, Q10, Q11, Q12, 26, 27 Q13, Q14, Q15 5, 6, 23, 24 V Power Positive supply pins. DD 9, 10, 19, 20 GND Power Power supply ground. 14 IN Input Pulldown Single-ended clock input. 5V tolerant. LVCMOS/LVTTL interface levels. Output enable pin. When LOW, forces outputs Q 8:13 to Hi-Z state. 15 OE0 Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. See Table 3. Output enable pin. When LOW, forces outputs Q 0:1 and Q 14:15 to 28 OE2 Input Pullup Hi-Z state. 5V tolerant. LVCMOS/LVTTL interface levels. See Table 3. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Power Dissipation Capacitance C = 3.465V 11 pF V PD DD (per output) NOTE 1 R Output Impedance V = 3.3V 15 OUT DD Rev C 3/20/15 2 LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER