8312 Low Skew, 1-to-12 LVCMOS/LVTTL Datasheet Fanout Buffer General Description Features The 8312 is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer Twelve LVCMOS/LVTTL outputs and a member of the family of High Performance Clock Solutions CLK input supports the following input types: LVCMOS, LVTTL from IDT. The 8312 single-ended clock input accepts LVCMOS or Maximum output frequency: 250MHz LVTTL input levels. The low impedance LVCMOS outputs are Output skew: 150ps (maximum) designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by Supply modes: Core/Output utilizing the ability of the outputs to drive two series terminated 3.3V/3.3V lines. 3.3V/2.5V The 8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/1.8V 2.5V/2.5V 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply 2.5V/1.8V modes. Guaranteed output and part-to-part skew characteristics 1.8V/1.8V along with the 1.8V output capabilities makes the 8312 ideal for 0C to 85C ambient operating temperature high performance, single ended applications that also require a limited output voltage. Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup CLK EN D 32 31 30 29 28 27 26 25 Q 1 GND 24 Q4 LE VDD 2 23 VDDO CLK EN 3 22 Q5 12 Pulldown CLK Q 0:11 GND CLK 4 21 GND 5 Q6 20 OE 6 VDDO 19 Pullup OE VDD 7 Q7 18 GND 8 GND 17 9 10 11 12 13 14 15 16 8312 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 2015 Integrated Device Technology, Inc 1 December 11, 2015 Q11 Q0 VDDO VDDO Q10 Q1 GND GND Q2 Q9 VDDO VDDO Q8 Q3 GND GND8312 Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 5, 8, 12, 16, GND Power Power supply ground. 17, 21, 25, 29 2, 7 V Power Positive supply pins. DD Synchronous control for enabling and disabling clock outputs. 3 CLK EN Input Pullup LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Q 0:11 . 6 OE Input Pullup LVCMOS / LVTTL interface levels. 9, 11, 13, 15, Q11, Q10, Q9, Q8, 18, 20, 22, 24, Q7, Q6, Q5, Q4, Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 26, 28, 30, 32 Q3, Q2, Q1, Q0 10, 14, 19, 23, V Power Output supply pins. DDO 27, 31 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Input Pullup Resistor 51 k R PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 19 pF DDO Power Dissipation Capacitance C = 2.625V 18 pF V PD DDO (per output) V = 2V 16 pF DDO V = 3.3V 5% 7 DDO R Output Impedance V = 2.5V 5% 7 OUT DDO V = 1.8V 0.2V 10 DDO 2015 Integrated Device Technology, Inc 2 December 11, 2015