Low Skew, 1-to-4, Crystal-to-LVCMOS/ 83904-02 Data Sheet LVTTL Fanout Buffer GENERAL DESCRIPTION FEATURES The 83904-02 is a low skew, high performance 1-to-4 Crystal-to- Four LVCMOS/LVTTL outputs, LVCMOS Fanout Buffer. The 83904-02 has selectable single-ended 19 typical output impedance V = V = 3.3V DD DDO clock or two crystal-oscillator inputs. There is an output enable to Two Crystal oscillator input pairs disable the outputs by placing them into a high-impedance state. One LVCMOS/LVTTL clock input Guaranteed output and part-to-part skew characteristics Crystal input frequencry range: 12MHz 38.88MHz make the 83904-02 ideal for those applications demand- Output frequency: 200MHz (maximum) ing well de ned performance and repeatability. Output Skew: 40ps (maximum) V = V = 3.3V DD DDO RMS phase jitter 25MHz output, using a 25MHz crystal (100Hz 1MHz): 0.16ps (typical) V = V = 3.3V DD DDO RMS phase noise at 25MHz: Offset Noise Power 100Hz ..............-118.4 dBc/Hz 1kHz ..............-141.5 dBc/Hz 10kHz ..............-157.2 dBc/Hz 100kHz ..............-157.2 dBc/Hz Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V 0C to 70C ambient operating temperature BLOCK DIAGRAM Available in lead-free (RoHS 6) package Pullup OE Pulldown CLK SEL0 Pulldown CLK SEL1 PIN ASSIGNMENT XTAL IN0 OSC Q0 CLK SEL0 1 16 VDDO 0 0 15 XTAL OUT0 2 Q0 XTAL OUT0 XTAL IN0 3 14 Q1 VDD 4 13 GND Q1 XTAL IN1 5 12 Q2 XTAL OUT1 6 11 Q3 10 CLK SEL1 7 VDDO XTAL IN1 CLK 8 9 OE OSC 0 1 Q2 83904-02 XTAL OUT1 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body 1 0 Pulldown Q3 CLK 1 1 G Package Top View 2016 Integrated Device Technology, Inc 1 Revision A March 17, 201683904-02 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description CLK SEL0, Clock select inputs. See Table 3, Input Reference Function Table. 1, 7 Input Pulldown CLK SEL1 LVCMOS / LVTTL interface levels. XTAL OUT0, Crystal oscillator interface. XTAL IN0 is the input. 2, 3 Input XTAL IN0 XTAL OUT0 is the output. 4V Power Positive supply pin. DD XTAL IN1, Crystal oscillator interface. XTAL IN1 is the input. 5, 6 Input XTAL OUT1 XTAL OUT1 is the output. 8 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. 9 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. 10, 16 V Power Output supply pins. DDO 11, 12, 14, 15 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 13 GND Power Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 8 pF DDO Power Dissipation Capacitance C V = 2.625V 7 pF PD DDO (per output) V = 2.0V 7 pF DDO V = 3.3V 19 DDO R Output Impedance V = 2.5V 21 OUT DDO V = 1.8V 32 DDO TABLE 3. INPUT REFERENCE FUNCTION TABLE Control Inputs Reference CLK SEL1 CLK SEL0 0 0 XTAL0 (default) 0 1 XTAL1 1 0 CLK 1 1 CLK 2016 Integrated Device Technology, Inc 2 Revision A March 17, 2016