XTAL IN0 Q3 CLK Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL 83904I-02 Fanout Buffer Datasheet General Description Features The 83904I-02 is a low skew, high performance 1-to-4 Crystal- Four LVCMOS / LVTTL outputs, 19 output impedance at to-LVCMOS Fanout Buffer. The 83904I-02 has selectable V = V = 3.3V DD DDO single-ended clock or two crystal-oscillator inputs. There is an output Two crystal oscillator input pairs enable to disable the outputs by placing them into a high-impedance LVCMOS / LVTTL clock input state. Crystal input frequency range: 12MHz 38.88MHz Guaranteed output and part-to-part skew characteristics make the Output frequency: 200MHz (maximum) 83904I-02 ideal for those applications demanding well defined performance and repeatability. Output skew: 40ps (maximum) at V = V = 3.3V DD DDO RMS phase jitter 25MHz output, using a 25MHz crystal, (100Hz 1MHz): 0.16ps (typical) at V = V = 3.3V DD DDO RMS phase noise at 25MHz Offset Noise Power 100Hz .............. -118.4 dBc/Hz 1kHz................. -141.5 dBc/Hz 10kHz............... -157.2 dBc/Hz 100kHz............. -157.2 dBc/Hz Power Supply Voltage Modes: Core / Output 3.3V / 3.3V 3.3V / 2.5V 3.3V / 1.8V 2.5V / 2.5V 2.5V / 1.8V Block Diagram -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packaging Pullup OE Pulldown CLK SEL0 Pulldown CLK SEL1 Pin Assignment XTAL IN0 1 16 VDDO OSC CLK SEL0 Q0 0 0 15 Q0 XTAL OUT0 2 14 Q1 3 XTAL OUT0 13 VDD 4 GND Q1 12 Q2 XTAL IN1 5 XTAL OUT1 6 11 VDDO XTAL IN1 CLK SEL1 7 10 OSC 8 9 OE 0 1 Q2 XTAL OUT1 83904I-02 16-Lead TSSOP 1 0 4.4mm x 5.0mm x 0.92mm package body Pulldown Q3 CLK 1 1 G Package Top View 2016 Integrated Device Technology, Inc. 1 Revision B, April 8, 201683904I-02 Datasheet Pin Descriptions and Pin Characteristics Table 1. Pin Descriptions Number Name Type Description 1, CLK SEL0, Clock select inputs. See Table 3, Input Reference Function Table. Input Pulldown 7 CLK SEL1 LVCMOS/LVTTL interface levels. 2. XTAL OUT0, Crystal oscillator interface. XTAL IN0 is the input. XTAL OUT0 is the Input 3 XTAL IN0 output. 4V Power Power supply pin. DD 5, XTAL IN1, Crystal oscillator interface. XTAL IN1 is the input. XTAL OUT1 is the Input 6 XTAL OUT1 output. 8 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable pin. When LOW, outputs are in high-impedance state. 9 OE Input Pullup When HIGH, outputs are active. LVCMOS/LVTTL interface levels. 10, 16 V Power Output supply pins. DDO 11, 12, 14, 15 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 13 GND Power Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 8 pF DDO Power Dissipation C Capacitance V = 2.625V 7 pF PD DDO (per output) = 2.0V 7 pF V DDO V = 3.3V 19 DDO R Output Impedance V = 2.5V 21 OUT DDO V = 1.8V 32 DDO Function Table Table 3. Input Reference Function Table Control Inputs CLK SEL1 CLK SEL0 Reference 0 0 XTAL0 (default) 0 1 XTAL1 10 CLK 11 CLK 2016 Integrated Device Technology, Inc. 2 Revision B, April 8, 2016