VDD Low Skew, 1:6 Crystal Interface to 83905I LVCMOS/ LVTTL Fanout Buffer Datasheet General Description Features The 83905I is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer. Six LVCMOS / LVTTL outputs The low impedance LVCMOS/LVTTL outputs are designed to Outputs able to drive 12 series terminated lines drive 50 series or parallel terminated transmission lines. The Crystal Oscillator Interface effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. Crystal input frequency range: 10MHz to 40MHz The 83905I is characterized at full 3.3V, 2.5V, and 1.8V, mixed Output skew: 80ps (maximum) 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply RMS phase jitter 25MHz, (100Hz 1MHz): 0.26ps (typical), modes. Guaranteed output and part-to-part skew characteristics V = V = 2.5V DD DDO along with the 1.8V output capabilities makes the 83905I ideal for Offset Noise Power high performance, single ended applications that also require a 100Hz.................-129.7 dBc/Hz limited output voltage. 1kHz...................-144.4 dBc/Hz 10kHz.................-147.3 dBc/Hz 100kHz...............-157.3 dBc/Hz 5V tolerant enable inputs Synchronous output enables Operating power supply modes: Full 3.3V, 2.5V, 1.8V Mixed 3.3V core/2.5V output operating supply Mixed 3.3V core/1.8V output operating supply Mixed 2.5V core/1.8V output operating supply -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Pin Assignments Block Diagram XTAL OUT 1 16 XTAL IN BCLK0 ENABLE2 2 15 ENABLE1 GND 3 14 BCLK5 BCLK0 4 13 VDDO 12 V 5 BCLK4 BCLK1 DDO XTAL IN BCLK1 6 11 GND GND 10 BCLK3 7 8 9 BCLK2 BCLK2 XTAL OUT 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm BCLK3 package body G Package BCLK4 Top View ENABLE 1 SYNCHRONIZE BCLK5 ENABLE 2 SYNCHRONIZE 2016 Integrated Device Technology, Inc. 1 Revision C September 28, 201683905I Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 XTAL OUT Output Crystal oscillator interface. XTAL OUT is the output. 2 ENABLE2 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3. 3 GND Power Power supply ground. 4 BCLK0 Output Clock output. LVCMOS/LVTTL interface levels. Power Output supply pin. 5V DDO 6 BCLK1 Output Clock output. LVCMOS/LVTTL interface levels. 7 GND Power Power supply ground. 8 BCLK2 Output Clock output. LVCMOS/LVTTL interface levels. Power Power supply pin. 9V DD 10 BCLK3 Output Clock output. LVCMOS/LVTTL interface levels. 11 GND Power Power supply ground. 12 BCLK4 Output Clock output. LVCMOS/LVTTL interface levels. Power Output supply pin. 13 V DDO 14 BCLK5 Output Clock output. LVCMOS/LVTTL interface levels. 15 ENABLE1 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3. 16 XTAL IN Input Crystal oscillator interface. XTAL IN is the input. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN = 3.465V 19 pF V DDO Power Dissipation C Capacitance V = 2.625V 18 pF PD DDO (per output) V = 2.0V 16 pF DDO V = 3.3V 5% 7 DDO R Output Impedance V = 2.5V 5% 7 OUT DDO V = 1.8V 0.2V 10 DDO 2016 Integrated Device Technology, Inc. 2 Revision C September 28, 2016