Low Skew, 1-to-8 Crystal-to-LVCMOS 83908I-02 Data Sheet Fanout Buffer GENERAL DESCRIPTION FEATURES Eight LVCMOS/LVTTL outputs , The 83908I-02 is a low skew, high performance 1-to-8 19 typical output impedance V = V = 3.3V Crystal Oscillator//Crystal-to-LVCMOS fanout buffer from DD DDO IDT. The 83908I-02 has selectable single-ended clock Two Crystal oscillator input pairs or two crystal-oscillator inputs. There is an output enable to One LVCMOS/LVTTL clock input disable the outputs by placing them into a high-impedance state. Crystal input frequency range: 10MHz - 40MHz Guaranteed output and part-to-part skew characteristics make Output frequency: 200MHz (typical) the 83908I-02 ideal for those applications demanding well de ned Output Skew: 70ps (maximum) V = V = 3.3V DD DDO performance and repeatability. Part-to-part skew: 700ps (maximum) V = V = 3.3V DD DDO RMS phase jitter 25MHz output using a 25MHz crystal (12kHz - 10MHz): 0.39ps (typical) V = V = 3.3V DD DDO Offset Noise Power 100Hz ..............-111.4 dBc/Hz 1kHz ..............-139.9 dBc/Hz 10kHz ..............-157.3 dBc/Hz 100kHz ..............-157.5 dBc/Hz Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM Pullup OE Pulldown CLK SEL0 Pulldown CLK SEL1 PIN ASSIGNMENT VDD 24 GND 1 XTAL IN0 XTAL IN0 2 23 XTAL IN1 OSC XTAL OUT0 3 XTAL OUT1 22 0 0 VDDO VDDO 4 21 Q0 20 Q7 5 XTAL OUT0 Q1 6 Q6 Q0 19 GND 7 GND 18 Q2 Q5 8 17 Q3 Q4 9 16 VDDO 10 VDDO 15 XTAL IN1 CLK SEL0 CLK SEL1 OSC 11 14 8 LVCMOS Outputs CLK 12 OE 0 1 13 XTAL OUT1 83908I-02 24-Lead, 173-MIL TSSOP Q7 4.4mm x 7.8mm x 0.925mm 1 0 Pulldown body package CLK 1 1 G Package Top View 2016 Integrated Device Technology, Inc 1 Revision A March 17, 201683908I-02 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Power supply pin. DD XTAL IN0, Crystal oscillator interface. XTAL IN0 is the input. 2, 3 Input XTAL OUT0 XTAL OUT0 is the output. 4, 10, 15, 21 V Power Output supply pins. DDO 5, 6, 8, Q0, Q1, Q2, Q3, 9, 16, 17, Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. Q4, Q5, Q6, Q7 19, 20 7, 18, 24 GND Power Power supply ground. 11, CLK SEL0, Clock select inputs. See Table 3, Input Reference Function Table. Input Pulldown 14 CLK SEL1 LVCMOS / LVTTL interface levels. 12 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. 13 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. XTAL OUT1, Crystal oscillator interface. XTAL IN1 is the input. 22, 23 Input XTAL IN1 XTAL OUT1 is the output. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN V = 3.465V 7 pF DDO Power Dissipation Capacitance C V = 2.625V 7 pF PD DDO (per output) V = 2V 6 pF DDO V = 3.3V 5% 19 DDO R Output Impedance V = 2.5V 5% 21 OUT DDO V = 1.8V 0.2V 32 DDO TABLE 3. INPUT REFERENCE FUNCTION TABLE Control Inputs Reference CLK SEL1 CLK SEL0 0 0 XTAL0 enabled (default) XTAL1 disabled 0 1 XTAL1 enabled XTAL0 disabled 1 0 CLK enabled XTAL0 and XTAL1 disabled 1 1 CLK enabled XTAL0 and XTAL1 disabled 2016 Integrated Device Technology, Inc 2 Revision A March 17, 2016