85102 Low Skew, 1-to-2, Differential/LVCMOS- to-0.7V HCSL Fanout Buffer DATA SHEET GENERAL DESCRIPTION FEATURES The 85102I is a low skew, high performance 1-to-2 Differen- Two 0.7V differential HCSL outputs tial-to-HCSL fanout buffer. The 85102I has a differential clock input. Selectable differential CLK0, nCLK0 or LVCMOS inputs The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate CLK0, nCLK0 pair can accept the following differential runt clock pulses on the output during asynchronous assertion/ input levels: LVPECL, LVDS, LVHSTL, HCSL deassertion of the clock enable pin. CLK1 can accept the following input levels: LVCMOS or LVTTL Guaranteed output and part-to-part skew characteristics make the 85102I ideal for those applications demanding well de ned Maximum output frequency: 500MHz performance and repeatability. Translates any single-ended input signal to 3.3V HCSL levels with resistor bias on nCLK input Output skew: 65ps (maximum) Part-to-part skew: 600ps (maximum) Propagation delay: 3.2ns (maximum) Additive phase jitter, RMS: 0.14ps typical 250MHz 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 1 16 CLK EN GND 15 Pullup CLK SEL 2 VDD CLK EN D 3 14 CLK0 Q0 Q 4 13 nCLK0 nQ0 Pulldown LE CLK0 CLK1 5 12 Q1 Pullup/Pulldown 0 nCLK0 6 11 Q0 nc nQ1 nQ0 10 nc 7 VDD Pulldown CLK1 8 9 1 IREF VDD Q1 nQ1 Pulldown CLK SEL 85102I 16-Lead TSSOP IREF 4.4mm x 5.0mm x 0.925mm body package G Package Top View 85102 REVISION B DECEMBER 19, 2014 1 85102 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description Synchronizing clock enable. When HIGH, clock outputs follow clock input. 1 CLK EN Input Pullup When LOW, Qx outputs are forced low, nQx outputs are forced high. LVTTL / LVCMOS interface levels. Clock select input. When HIGH, selects CLK1 input. 2 CLK SEL Input Pulldown When LOW, selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. Pullup/ 4 nCLK0 Input Inverting differential clock input. Pulldown 5 CLK1 Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels. 6, 7 nc Unused No connect. An external xed resistor (475) from this pin to ground provides a refer- 8 IREF Input ence current used for differential current-mode Qx/nQx clock outputs. 9, 10, 15 V Power Positive supply pins. DD 11, 12 nQ1, Q1 Output Differential output pair. HCSL interface levels. 13, 14 nQ0, Q0 Output Differential output pair. HCSL interface levels. 16 GND Power Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Low Skew, 1-to-2, Differential/LVCMOS-to-0.7V HCSL 2 REVISION B 12/19/14 Fanout Buffer