Low Skew, 1-to-4, Differential/LVCMOS-to- 85104I Data Sheet 0.7V HCSL Fanout Buffer GENERAL DESCRIPTION FEATURES The 85104I is a low skew, high performance 1-to-4 Differential/ Four 0.7V differential HCSL outputs LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two select- Selectable differential CLK0, nCLK0 or LVCMOS inputs able clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS CLK0, nCLK0 pair can accept the following differential or LVTTL input levels. The clock enable is internally synchronized input levels: LVPECL, LVDS, LVHSTL, HCSL to eliminate runt clock pulses on the outputs during asynchronous CLK1 can accept the following input levels: assertion/deassertion of the clock enable pin. LVCMOS or LVTTL Guaranteed output and part-to-part skew characteristics Maximum output frequency: 500MHz make the 85104I ideal for those applications demanding well Translates any single-ended input signal to 3.3V de ned performance and repeatability. HCSL levels with resistor bias on nCLK input Output skew: 100ps (maximum) Part-to-part skew: 600ps (maximum) Propagation delay: 3.2ns (maximum) Additive phase jitter, RMS: 0.22ps (typical) 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT Pullup CLK EN D Q Pulldown LE CLK0 Pullup/Pulldown 0 nCLK0 Q0 nQ0 Pulldown CLK1 1 Q1 nQ1 Pulldown CLK SEL 85104I 20-Lead TSSOP Q2 nQ2 6.5mm x 4.4mm x 0.925mm Package Body IREF G Package Q3 Top View nQ3 2016 Integrated Device Technology, Inc 1 Revision A January 20, 201685104I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 GND Power Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2 CLK EN Input Pullup When LOW, Qx outputs are forced low, nQx outputs are forced high. LVTTL / LVCMOS interface levels. Clock select input. When HIGH, selects CLK1 input. 3 CLK SEL Input Pulldown When LOW, selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels. 4 CLK0 Input Pulldown Non-inverting differential clock input. Pullup/ 5 nCLK0 Input Inverting differential clock input. Pulldown 6 CLK1 Input Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels. 7, 8 nc Unused No connect. An external xed precision resistor (475) from this pin to ground provides a 9 IREF Input reference current used for differential current-mode Qx/nQx outputs. 10, 13, 18 V Power Positive supply pins. DD 11, 12 nQ3, Q3 Output Differential output pair. HCSL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. HCSL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. HCSL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision A January 20, 2016