nCLK nCLK nQ5 nQ4 Low Skew, 1-to-8, Differential-to-0.7V 85108 HCSL Clock Distribution Chip DATA SHEET General Description Features The 85108 is a low skew, high performance 1-to-8 Eight 0.7V differential HCSL clock output pairs Differential-to-0.7V HCSL Clock Distribution Chip. The 85108 CLK, CLK/nCLK input pair can accept the following differential input nCLK pair can accept most differential input levels and translates levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL them to 3.3V HCSL output levels. The 85108 provides a low power, Maximum output frequency: 500MHz low noise, low skew, point-to-point solution for distributing HCSL Additive phase jitter, RMS: 0.09ps (typical) clock signals. Output skew: 80ps (maximum) Guaranteed output and part-to-part skew specifications make the Part-to-part skew: 400ps (maximum) 85108 ideal for those applications demanding well defined performance and repeatability. Propagation delay: 3ns (maximum) Full 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Q0 1 24 Q7 Q0 nQ0 2 23 nQ7 nQ0 V 3 22 GND DD Q1 CLK 4 21 V DD nQ1 5 20 Q6 Q2 Q1 6 19 nQ6 nQ2 nQ1 7 18 Q5 Q2 8 17 Q3 nQ2 9 16 V DD Pulldown nQ3 CLK IREF 10 15 GND Pullup/Pulldown Q4 Q3 Q4 11 14 nQ4 nQ3 12 13 IREF Q5 nQ5 85108 Q6 24-Lead TSSOP, 173-MIL nQ6 4.4mm x 7.8mm x 0.925mm package body Q7 G Package nQ7 Top View 85108 Rev A 6/11/15 1 2015 Integrated Device Technology, Inc.85108 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. HCSL interface levels. 3, 16, 21 V Power Power supply pins. DD 4 CLK Input Pulldown Non-inverting differential clock input. Pullup/ 5 nCLK Input Inverting differential clock input. Pulldown 6, 7 Q1, nQ1 Output Differential output pair. HCSL interface levels. 8, 9 Q2, nQ2 Output Differential output pair. HCSL interface levels. External fixed precision resistor (475 ) from this pin to ground provides a reference 10 IREF current used for differential current-mode Qx/nQx clock outputs. 11, 12 Q3, nQ3 Output Differential output pair. HCSL interface levels. 13, 14 nQ4, Q4 Output Differential output pair. HCSL interface levels. 15, 22 GND Power Power supply ground. 17, 18 nQ5, Q5 Output Differential output pair. HCSL interface levels. 19, 20 nQ6, Q6 Output Differential output pair. HCSL interface levels. 23, 24 nQ7, Q7 Output Differential output pair. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistors 51 k PULLUP R Input Pulldown Resistors 51 k PULLDOWN Function Tables Table 3. Clock Input Function Table Inputs Outputs CLK nCLK Q 0:7 n 0:7 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting 0 Biased NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting 1 Biased NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting Biased NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting Biased NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting NOTE 1: Please refer to the Application Information section Wiring the Differential Input to Accept Single Ended Levels. LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-0.7V HCSL CLOCK 2 Rev A 6/11/15 DISTRIBUTION CHIP