Low Skew, 1-to-16 ICS8516 Differential-to-LVDS Clock Distribution Chip DATASHEET GENERAL DESCRIPTION FEATURES The ICS8516 is a low skew, high performance 1-to-16 Differential- Sixteen differential LVDS outputs to-LVDS Clock Distribution Chip. The ICS8516 CLK, nCLK pair can CLK, nCLK pair can accept the following differential accept any differential input levels and translates them to 3.3V LVDS input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516 provides a low power, low noise, point-to-point Maximum output frequency: 700MHz solution for distributing clock signals over controlled impedances Translates any differential input signal (LVPECL, LVHSTL, of 100. SSTL, DCM) to LVDS levels without external bias networks Dual output enable inputs allow the ICS8516 to be used in a Translates any single-ended input signal to LVDS 1-to-16 or 1-to-8 input/output mode. with resistor bias on nCLK input Guaranteed output and part-to-part skew speci cations make Multiple output enable inputs for disabling unused the ICS8516 ideal for those applications demanding well outputs in reduced fanout applications de ned performance and repeatability. LVDS compatible Output skew: 90ps (maximum) Part-to-part skew: 500ps (maximum) Propagation delay: 2.4ns (maximum) Additive phase jitter, RMS: 148fs (typical) 3.3V operating supply 0C to 70C ambient operating temperature Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT 48-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View 8516 REVISION B 6/11/15 1 2015 Integrated Device Technology, Inc.8516 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 6, 12, V Power Positive supply pins. DD 25, 31, 36 2, 3 nQ5, Q5 Output Differential output pair. LVDS interface levels. 4, 5 nQ4, Q4 Output Differential output pair. LVDS interface levels. 7, 17, 20, GND Power Power supply ground. 30, 41, 44 8, 9 nQ3, Q3 Output Differential output pair. LVDS interface levels. 10, 11 nQ2, Q2 Output Differential output pair. LVDS interface levels. 13, 14 nQ1, Q1 Output Differential output pair. LVDS interface levels. 15, 16 nQ0, Q0 Output Differential output pair. LVDS interface levels. 18 nCLK Input Pullup Inverting differential clock input. 19 CLK Input Pulldown Non-inverting differential clock input. 21, 22 Q15, nQ15 Output Differential output pair. LVDS interface levels. 23, 24 Q14, nQ14 Output Differential output pair. LVDS interface levels. 26, 27 Q13, nQ13 Output Differential output pair. LVDS interface levels. 28, 29 Q12, nQ12 Output Differential output pair. LVDS interface levels. 32, 33 Q11, nQ11 Output Differential output pair. LVDS interface levels. 34, 35 Q10, nQ10 Output Differential output pair. LVDS interface levels. 37, 38 Q9, nQ9 Output Differential output pair. LVDS interface levels. 39, 40 Q8, nQ8 Output Differential output pair. LVDS interface levels. Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15 OE1 42, 43 OE2, OE1 Input Pullup controls outputs Q0, nQ0 thru Q7, nQ7. LVCMOS/LVTTL interface levels. 45, 46 nQ7, Q7 Output Differential output pair. LVDS interface levels. 47, 48 nQ6, Q6 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. LOW SKEW, 1-TO-16 2 REVISION B 6/11/15 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP