Low Skew, 1-to-10 Differential-to-3.3V, 85310I-11 2.5V LVPECL/ECL Fanout Buffer DATA SHEET General Description Features The 85310I-11 is a low skew, high performance 1-to-10 Ten differential 2.5V, 3.3V LVPECL/ECL output pair Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer. The CLKx, Two selectable differential input pairs nCLKx pairs can accept most standard differential input levels. The Differential CLKx, nCLKx pairs can accept the following interface 85310I-11 is characterized to operate from either a 2.5V or a 3.3V levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL power supply. Guaranteed output and part-to-part skew Maximum output frequency: 700MHz characteristics make the 85310I-11 ideal for those clock distribution Translates any single ended input signal to 3.3V LVPECL levels applications demanding well defined performance and repeatability. with resistor bias on nCLK input Output skew: 30ps (typical) Part-to-part skew: 140ps (typical) Propagation delay: 2ns (typical) Additive phase jitter, RMS: <0.13ps (typical) LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.8V to -2.375V CC EE -40C to 85C ambient operating temperature Available in lead-free RoHS compliant package Pin Assignment Block Diagram Q0 Pulldown nQ0 CLK0 Pullup 0 nCLK0 Q1 32 31 30 29 28 27 26 25 Pulldown nQ1 CLK1 VCC 1 Q3 24 Pullup 1 nCLK1 Q2 CLK SEL 2 23 nQ3 nQ2 CLK0 3 22 Q4 Q3 Pulldown CLK SEL nQ4 nCLK0 4 21 nQ3 CLK EN Q5 5 20 Q4 nQ4 CLK1 6 nQ5 19 Pullup CLK EN D Q5 nCLK1 7 18 Q6 Q nQ5 LE VEE 8 17 nQ6 Q6 9 10 11 12 13 14 15 16 nQ6 Q7 nQ7 85310I-11 Q8 nQ8 32-Lead LQFP Q9 7mm x 7mm x 1.4mm package body nQ9 Y Package Top View 85310I-11 Rev F 7/8/15 1 2015 Integrated Device Technology, Inc. VCCO VCCO nQ9 Q0 Q9 nQ0 nQ8 Q1 Q8 nQ1 nQ7 Q2 Q7 nQ2 VCCO VCCO85310I-11 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1V Power Positive supply pin. CC Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, 2 CLK SEL Input Pulldown selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. 5 CLK EN Input Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. 6 CLK1 Input Pulldown Non-inverting differential clock input. 7 nCLK1 Input Pullup Inverting differential clock input. 8V Power Negative supply pin. EE 9, 16, 25, 32 V Power Output supply pins. CCO 10, 11 nQ9, Q9 Output Differential output pair. LVPECL interface levels. 12, 13 nQ8, Q8 Output Differential output pair. LVPECL interface levels. 14, 15 nQ7, Q7 Output Differential output pair. LVPECL interface levels. 17, 18 nQ6, Q6 Output Differential output pair. LVPECL interface levels. 19, 20 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 28, 29 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Input Pullup Resistor 51 k R PULLUP R Input Pulldown Resistor 51 k PULLDOWN LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL 2 Rev F 7/8/15 FANOUT BUFFER