CLK0 Low Skew, 1-to-5 Differential-to-2.5V, 3.3V ICS85314I-11 LVPECL Fanout Buffer DATA SHEET General Description Features The ICS85314I-11 is a low skew, high performance 1-to-5 Five differential 2.5V/3.3V LVPECL outputs Differential-to-2.5V, 3.3V LVPECL fanout buffer. The ICS85314I-11 Selectable differential CLKx, nCLKx inputs has two selectable differential clock inputs. The CLK0, nCLK0 and CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following CLK1, nCLK1 pairs can accept most standard differential input differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL levels. The clock enable is internally synchronized to eliminate runt Maximum output frequency: 700MHz clock pulses on the outputs during asynchronous assertion/ Translates any single-ended input signal to 3.3V deassertion of the clock enable pin. LVPECL levels with resistor bias on nCLK input Guaranteed output and part-to-part skew characteristics make the Output skew: 30ps (maximum) ICS85314I-11 ideal for those applications demanding well defined Propagation delay: 1.8ns (maximum) performance and repeatability. LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment Pulldown nCLK EN Q0 1 20 VCC D nQ0 2 19 nCLK EN Q Q1 3 18 VCC CK nQ1 4 17 nCLK1 Q2 5 16 CLK1 Pulldown CLK0 Pullup 0 nQ2 6 15 RESERVED nCLK0 Q0 Q3 7 14 nCLK0 Pulldown nQ0 CLK1 nQ3 8 13 Pullup 1 nCLK1 Q4 9 12 CLK SEL Q1 nQ4 10 11 VEE nQ1 ICS85314I-11 Q2 Pulldown nQ2 CLK SEL 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body Q3 G Package nQ3 Top View Q4 nQ4 ICS85314I-11 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View ICS85314AGI-11 REVISION F SEPTEMBER 16, 2013 1 2013 Integrated Device Technology, Inc.ICS85314I-11 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11 V Power Negative supply pin. EE Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, 12 CLK SEL Input Pulldown selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels. 13 CLK0 Input Pulldown Non-inverting differential clock input. 14 nCLK0 Input Pullup Inverting differential clock input. 15 RESERVED Reserve Reserved pin. 16 CLK1 Input Pulldown Non-inverting differential clock input. 17 nCLK1 Input Pullup Inverting differential clock input. Power Positive supply pins. 18, 20 V CC Synchronizing clock enable. When LOW, clock outputs follow clock input. When 19 nCLK EN Input Pulldown HIGH, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS85314AGI-11 REVISION F SEPTEMBER 16, 2013 2 2013 Integrated Device Technology, Inc.