Low Skew, 1-to-9, Differential-to- 8531-01 Data Sheet 3.3V LVPECL Fanout Buffer GENERAL DESCRIPTION FEATURES The 8531-01 is a low skew, high performance Nine differential 3.3V LVPECL outputs 1-to-9 Differential-to-3.3V LVPECL Fanout Selectable differential CLK, nCLK or LVPECL clock inputs Buffer and a member of the family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept the following differential 8531-01 has two selectable clock inputs. The CLK, input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL nCLK pair can accept most standard differential input PCLK, nPCLK supports the following input types: levels. The PCLK, nPCLK pair can accept LVPECL, CML, or LVPECL, CML, SSTL SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous Maximum output frequency: 500MHz assertion/deassertion of the clock enable pin. Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input Guaranteed output skew and part-to-part skew character- istics make the 8531-01 ideal for high performance work- Additive phase jitter, RMS: 0.17ps (typical) station and server applications. Output skew: 50ps (maximum) Part-to-part skew: 250ps (maximum) Propagation delay: 2ns (maximum) 3.3V operating supply 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Industrial Temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View 2016 Integrated Device Technology, Inc 1 Revision F January 19, 20168531-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Power supply pin. CC 2 CLK Input Pulldown Non-inverting differential clock input. 3 nCLK Input Pullup Inverting differential clock input. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. 4 CLK SEL Input Pulldown When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 6 nPCLK Input Pullup Inverting differential LVPECL clock input. 7V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. 8 CLK EN Input Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. 9, 16, 17, V Power Output supply pins. CCO 24, 25, 32 10, 11 nQ8, Q8 Output Differential output pair. LVPECL interface level. 12, 13 nQ7, Q7 Output Differential output pair. LVPECL interface level. 14, 15 nQ6, Q6 Output Differential output pair. LVPECL interface level. 18, 19 nQ5, Q5 Output Differential output pair. LVPECL interface level. 20, 21 nQ4, Q4 Output Differential output pair. LVPECL interface level. 22, 23 nQ3 Q3 Output Differential output pair. LVPECL interface level. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface level. 28, 29 nQ1, Q1 Output Differential output pair. LVPECL interface level. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface level. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision F January 19, 2016