LVCMOS/LVTTL-to-Differential 85320 3.3V, 2.5V LVPECL Translator DATASHEET GENERAL DESCRIPTION FEATURES The 85320I is a LVCMOS / LVTTL-to-Differential 3.3V, 2.5V LVPECL One differential 2.5V/3.3V LVPECL output translator. The 85320I has a single ended clock input. The single LVCMOS/LVTTL CLK input ended clock input accepts LVCMOS or LVTTL input levels and translates them to 3.3V or 2.5V LVPECL levels. The small outline CLK accepts the following input levels: LVCMOS or LVTTL 8-pin SOIC package makes this device ideal for applications where Maximum output frequency: 267MHz space, high performance and low power are important. Part-to-part skew: 275ps (maximum) Additive phase jitter, RMS: 0.05ps (typical) 3.3V operating supply voltage (operating range 3.135V to 3.465V) 2.5V operating supply voltage (operating range 2.375V to 2.625V) -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT Q nc 1 8 VCC CLK nQ Q 2 7 CLK 3 6 nQ nc nc 4 5 VEE 85320I 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View 85320 REVISION B DECEMBER 19, 2014 1 2014 Integrated Device Technology, Inc.85320 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 4, 6 nc Unused No connect. 2,3 Q, nQ Output Differential output pair. LVPECL interface levels. 5V Power Negative supply pin. EE 7 CLK Input Pullup LVCMOS / LVTTL clock input. 8V Power Positive supply pin. CC NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP LVCMOS/LVTTL-TO-DIFFERENTIAL 2 REVISION B 12/19/14 3.3V, 2.5V LVPECL TRANSLATOR