Low Skew, 1-to-4 8533I-01 Differential-to-3.3V LVPECL Fanout Buffer DATA SHEET GENERAL DESCRIPTION FEATURES The 8533I-01 is a low skew, high performance 1-to-4 Four differential 3.3V LVPECL outputs Differential-to-3.3V LVPECL Fanout Buffer. The 8533I-01 has Selectable differential CLK, nCLK or LVPECL clock inputs two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair CLK, nCLK pair can accept the following differential can accept LVPECL, CML, or SSTL input levels. The clock input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL enable is internally synchronized to eliminate runt pulses on PCLK, nPCLK supports the following input types: the outputs during asynchronous assertion/deassertion of the LVPECL, CML, SSTL clock enable pin. Maximum output frequency: 650MHz Guaranteed output and part-to-part skew characteristics make Translates any single-ended input signal to 3.3V the 8533I-01 ideal for those applications demanding well de ned LVPECL levels with resistor bias on nCLK input performance and repeatability. Output skew: 30ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 1.5ns (maximum), CLK/nCLK Additive phase jitter, RMS: 0.060ps (typical) 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 8533I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View 8533I-01 REVISION A 7/9/15 1 2015 Integrated Device Technology, Inc.8533I-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. 2 CLK EN Input Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVC- MOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. 3 CLK SEL Input Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK Input Pullup Inverting differential LVPECL clock input. 8, 9 nc Unused No connect. 10, 13, 18 V Power Positive supply pins. CC 11, 12 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN LOW SKEW, 1-TO-4 2 REVISION A 7/9/15 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER