Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V ICS8535-01 LVPECL Fanout Buffer DATA SHEET General Description Features The ICS8535-01 is a low skew, high performance 1-to-4 Four differential 3.3V LVPECL outputs LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The ICS8535- 01 Selectable CLK0 or CLK1 inputs for redundant and multiple has two single ended clock inputs. the single ended clock input frequency fanout applications accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to CLK0 or CLK1 can accept the following input levels: eliminate runt clock pulses on the output during asynchronous LVCMOS or LVTTL assertion/deassertion of the clock enable pin. Maximum output frequency: 266MHz Guaranteed output and part-to-part skew characteristics make the Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels ICS8535-01 ideal for those applications demanding well defined performance and repeatability. Output skew: 30ps (maximum) Part-to-part skew: 250ps (maximum) Propagation delay: 1.9ns (maximum) Additive phase jitter, RMS: < 0.09ps (typical) Pin Assignment 3.3V operating supply V 1 20 Q0 EE 0C to 70C ambient operating temperature CLK EN 2 19 nQ0 CLK SEL 3 18 V CC Lead-free (RoHS 6) packaging CLK0 4 17 Q1 nc 5 16 nQ1 CLK1 6 15 Q2 nc 7 14 nQ2 nc 8 13 V CC nc 9 12 Q3 V 10 11 nQ3 Block Diagram CC ICS8535-01 D CLK EN 20-Lead TSSOP Q 4.4mm x 6.5mm x 0.92 body package LE G Package CLK0 0 Q0 nQ0 CLK1 Top View 1 Q1 nQ1 CLK SEL Q2 nQ2 20 18 19 17 16 V 1 15 V CC CC Q3 nQ3 nQ3 2 14 Q2 3 Q3 13 nQ2 4 V 12 V EE CC CLK EN 5 11 nc 6 7 8 9 10 ICS8535-01 20-Lead VFQFN 4mm x 4mm x 0.9 body package K Package Top View ICS8535-01 REVISION F 08/11/14 1 2014 Integrated Device Technology, Inc. CLK SEL Q0 CLK0 nQ0 nc Q1 CLK1 nQ1 nc V CCICS8535-01 DATA SHEET Pin Descriptions and Characteristics 1 Table 1. Pin Descriptions Name Type Description V Power Negative supply pin. EE Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, CLK EN Input Pullup Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. CLK SEL Input Pulldown LVCMOS / LVTTL interface levels. CLK0 Input Pulldown LVCMOS / LVTTL clock input. CLK1 Input Pulldown LVCMOS / LVTTL clock input. nc Unused No connect V Power Positive supply pins CC nQ3, Q3 Output Differential output pair. LVPECL interface levels. nQ2, Q2 Output Differential output pair. LVPECL interface levels. nQ1, Q1 Output Differential output pair. LVPECL interface levels. nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE 1: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4 pF C IN Input Pullup Resistor 51 k R PULLUP Input Pulldown Resistor 51 k R PULLDOWN LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL 2 REVISION F 08/11/14 FANOUT BUFFER