Low Skew, 1-to-6, Crystal/ LVCMOS/ ICS8536-01 Differential-to-3.3V, 2.5V LVPECL Fanout Buffer DATA SHEET GENERAL DESCRIPTION FEATURES Six 3.3V, 2.5V LVPECL outputs The ICS8536-01 is a low skew, high performance 1-to-6 Selectable Crystal, Single-Ended, or Differential Input-to- Selectable crystal oscillator, differential CLK1, nCLK1 pair 3.3V, 2.5V LVPECL Fanout Buffer. The ICS8536-01 has or LVCMOS/LVTTL clock input selectable crystal, single ended or differential clock inputs. CLK1, nCLK pair can accept the following differential The single ended clock input accepts LVCMOS or LVTTL input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels and translates them to LVPECL levels. The CLK1, nCLK1 pair can accept most standard differential Maximum output frequency: 700MHz input levels. The output enable is internally synchronized to Crystal frequency range: 12MHz - 40MHz eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Output skew: 55ps (maximum) CLK1, nCLK1 3.3V Guaranteed output and part-to-part skew characteristics Part-to-part skew: 450ps (maximum) make the ICS8536-01 ideal for those applications demanding Additive phase jitter, RMS: 0.19ps (typical) well defined performance and repeatability. Full 3.3V or 2.5V supply mode 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) packages PIN ASSIGNMENT BLOCK DIAGRAM Pullup 1 nQ2 24 Q3 CLK EN D Q2 2 23 nQ3 Q 3 22 VCC VCC LE Pulldown 4 CLK SEL0 nQ1 21 Q4 5 20 Q1 nQ4 Pulldown CLK SEL1 6 19 VEE VCC 7 18 nQ0 Q5 8 17 Q0 nQ5 XTAL IN 9 16 Q0 CLK SEL0 CLK SEL1 00 10 OSC 15 XTAL IN nCLK1 11 nQ0 14 XTAL OUT CLK1 XTAL OUT 12 13 CLK EN CLK0 Pulldown 6 LVPECL Outputs CLK0 01 ICS8536-01 Q5 Pulldown 24-Lead TSSOP CLK1 1X 4.40mm x 7.8mm x 0.925mm Pullup nQ5 nCLK1 package body G Package Top View ICS8536-01 REVISION B AUGUST 17, 2012 1ICS8536-01 Data Sheet CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 12, 2ntQ2, QO.utpu Differential output pair. LVPECL interface levels 3V, 19, 22P.ower Power supply pins CC 41, 5ntQ1, QO.utpu Differential output pair. LVPECL interface levels 6VP.ower Negative supply pin EE 70, 8ntQ0, QO.upu Differential output pair. LVPECL interface levels CLK SEL0, 9, 16 Innput Pulldow Clock select pins. LVCMOS/LVTTL interface levels. See Table 3B. CLK SEL1 XTAL IN, Parallel resonant crystal interface. XTAL OUT is the output, 10, 11 Input XTAL OUT XTAL IN is the input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. 1N2CtLK EIpnpu Pullu When LOW, the outputs are disabled. LVCMOS / LVTTL interface levels. See Table 3A. 103 CtLK InnpuP.ulldow LVCMOS/LVTTL clock input 114 CtLKInnpuP.ulldow Non-inverting differential clock input 115 ntCLKIpnpuP.ullu Inverting differential clock input 157, 18ntQ5, QO.utpu Differential output pair. LVPECL interface levels 240, 21ntQ4, QO.utpu Differential output pair. LVPECL interface levels 233, 24ntQ3, QO.utpu Differential output pair. LVPECL interface levels NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 4Fp IN R Input Pulldown Resistor 5k1 PULLDOWN R Input Pulup Resistor 5k1 PULLUP ICS8536AG-01 REVISION B AUGUST 17, 2012 2