Low Skew, 1-to-10, 853S111B Datasheet Differential-to-2.5V, 3.3V LVPECL/ECL Description Features The 853S111B is a low skew, high performance 1-to-10 Ten differential 2.5V, 3.3V LVPECL/ECL outputs Differential-to-2.5V/ 3.3V LVPECL/ECL Fanout Buffer. The Two selectable differential input pairs 853S111B is characterized to operate from either a 2.5V or a 3.3V PCLKx, nPCLKx pairs can accept the following power supply. differential input levels: LVPECL, LVDS, SSTL, CML Guaranteed output and part-to-part skew characteristics make the Maximum output frequency: 2.5GHz 853S111B ideal for those clock distribution applications demanding well defined performance and repeatability. Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input Output skew: 50ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 645ps (maximum) Additive Phase Jitter, RMS: 0.03ps (typical) LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE Pin Assignments ECL mode operating voltage supply range: V = 0V, V = -3.8V to -2.375V CC EE -40C to 85C ambient operating temperature 24 23 22 21 20 19 18 17 VCCO 25 VCCO 16 Available lead-free (RoHS 6) packaging nQ2 26 15 Q7 Supports 105C board temperature operations 853S111B Q2 27 14 nQ7 32-Lead TQFP, E-Pad Q8 nQ1 28 13 7mm x 7mm x 1mm Q1 nQ8 29 12 package body Block Diagram nQ0 30 Y Package Q9 11 Pulldown PCLK0 0 Pullup/Pulldown Top View Q0 31 Q0 10 nQ9 nPCLK0 VCCO nQ0 32 9 VCCO Pulldown PCLK1 1 2 3 4 5 6 7 8 1 Pullup/Pulldown nPCLK1 Q1 nQ1 Pulldown CLK SEL Q2 V BB nQ2 nQ3 nQ3 24 23 22 21 20 19 18 17 Q4 25 VCCO 16 VCCO nQ4 nQ2 26 15 Q7 853S111B Q5 Q2 27 nQ7 14 nQ5 32-Lead VFQFN Q8 nQ1 28 13 5mm x 5mm x 0.925mm Q6 Q1 29 12 nQ8 package body nQ6 nQ0 30 Q9 K Package 11 Q7 Top View Q0 31 nQ9 10 nQ7 VCCO 32 VCCO 9 1 2 3 4 5 6 7 8 nQ8 nQ8 Q9 nQ9 2017 Integrated Device Technology, Inc. 1 November 9, 2017 VCC VCC Q3 Q3 CLK SEL CLK SEL nQ3 nQ3 PCLK0 Q4 PCLK0 Q4 nQ4 nPCLK0 nQ4 nPCLK0 VBB Q5 VBB Q5 PCLK1 nQ5 PCLK1 nQ5 nPCLK1 nPCLK1 Q6 Q6 VEE VEE nQ6 nQ6853S111B Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1V Power Positive supply pin. CC Clock select input. When HIGH, selects PCLK1/nPCLK1 inputs. When 2 CLK SEL Input Pulldown LOW, selects PCLK0/nPCLK0 inputs. LVPECL interface levels. Also accepts standard LVCMOS input levels. 3 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 4 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 5V Output Bias voltage to be connected for single-ended applications. BB 6 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 7 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 8V Power Negative supply pin. EE 9, 16, 25, 32 V Power Output supply pins. CCO 10, 11 nQ9, Q9 Output Differential output pair. LVPECL/ECL interface levels. 12, 13 Output Differential output pair. LVPECL/ECL interface levels. nQ8, Q8 14, 15 Output Differential output pair. LVPECL/ECL interface levels. nQ7, Q7 17, 18 nQ6, Q6 Output Differential output pair. LVPECL/ECL interface levels. 19, 20 Output Differential output pair. LVPECL/ECL interface levels. nQ5, Q5 21, 22 Output Differential output pair. LVPECL/ECL interface levels. nQ4, Q4 23, 24 nQ3, Q3 Output Differential output pair. LVPECL/ECL interface levels. 26, 27 Output Differential output pair. LVPECL/ECL interface levels. nQ2, Q2 28, 29 Output Differential output pair. LVPECL/ECL interface levels. nQ1, Q1 30, 31 nQ0, Q0 Output Differential output pair. LVPECL/ECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pulldown Resistor 75 k PULLDOWN R RPullup/Pulldown Resistors 50 k VCC/2 2017 Integrated Device Technology, Inc. 2 November 9, 2017