nQ3 Low Skew, 1-to-4, ICS854104I Differential-to-LVDS Fanout Buffer DATASHEET General Description Features The ICS854104I is a low skew, high performance 1-to-4 Four differential LVDS output pairs Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage One differential clock input pair Differential Signaling (LVDS), the ICS854104I provides a low power, CLK/nCLK can accept the following differential input levels: low noise, solution for distributing clock signals over controlled LVPECL, LVDS, LVHSTL, HCSL, SSTL impedances of 100. The ICS854104I accepts a differential input level and translates it to LVDS output levels. Each output has an individual OE control Guaranteed output and part-to-part skew characteristics make the Maximum output frequency: 700MHz ICS854104I ideal for those applications demanding well defined Translates differential input signals to LVDS levels performance and repeatability. Additive phase jitter, RMS: 0.232ps (typical) Output skew: 50ps (maximum) Part-to-part skew: 350ps (maximum) Propagation delay: 1.3ns (maximum) 3.3V operating supply -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment Q0 OE0 Q0 1 16 OE1 2 nQ0 15 nQ0 OE2 3 14 Q1 Pullup OE0 V 4 13 nQ1 DD 5 12 Q2 GND Q1 CLK 6 11 nQ2 nCLK 7 10 Q3 nQ1 Pulldown CLK OE3 8 9 Pullup OE1 Pullup/Pulldown nCLK Q2 ICS854104 nQ2 16-LeadTSSOP Pullup OE2 4.4mm x 5.0mm x 0.925mm package body G Package Q3 TopView nQ3 Pullup OE3 ICS854104AGI REVISION B JANUARY 30, 2014 1 2014 Integrated Device Technology, Inc.ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL 1 OE0 Input Pullup interface levels. Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL 2 OE1 Input Pullup interface levels. Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL 3 OE2 Input Pullup interface levels. Power Positive supply pin. 4V DD 5 GND Power Power supply ground. 6 CLK Input Pulldown Non-inverting differential clock input. /2 default when left floating. 7 nCLK Input Pullup/Pulldown Inverting differential clock input. V DD Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL 8 OE3 Input Pullup interface levels. 9, 10 nQ3, Q3 Output Differential output pair. LVDS interface levels. 11, 12 nQ2, Q2 Output Differential output pair. LVDS interface levels. 13, 14 nQ1, Q1 Output Differential output pair. LVDS interface levels. 15, 16 nQ0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4 pF C IN Input Pullup Resistor 51 k R PULLUP Input Pulldown Resistor 51 k R PULLDOWN Function Table Table 3. Output Enable FunctionTable Inputs Outputs OE 3:0 Q 0:3 , nQ 0:3 0 High-Impedance 1 Active (default) ICS854104AGI REVISION B JANUARY 30, 2014 2 2014 Integrated Device Technology, Inc.