GND ICS8543I Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer DATA SHEET General Description Features The ICS8543I is a low skew, high performance 1-to-4 Differen- Four differential LVDS output pairs tial-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Selectable differential CLK/nCLK or LVPECL clock inputs Signaling (LVDS) the ICS8543I provides a low power, low noise, so- CLK/nCLK pair can accept the following differential input levels: lution for distributing clock signals over controlled impedances of LVPECL, LVDS, LVHSTL, SSTL, HCSL 100 . The ICS8543I has two selectable clock inputs. The CLK, PCLK/nPCLK pair can accept the following differential input nCLK pair can accept most standard differential input levels. The levels: LVPECL, CML, SSTL PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. Maximum output frequency: 650MHz The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the Translates any single-ended input signals to LVDS levels with resistor bias on nCLK input clock enable pin. Additive phase Jitter, RMS: 0.164ps (typical) Guaranteed output and part-to-part skew characteristics make the Output skew: 40ps (maximum) ICS8543I ideal for those applications demanding well defined perfor- mance and repeatability. Part-to-part skew: 600ps (maximum) Propagation delay: 2.6ns (maximum) Full 3.3Vsupply mode -40C to 85C ambient operating temperature Available in lead-free packages Block Diagram Pin Assignment Pullup GND 1 20 Q0 CLK EN D CLK EN 2 19 nQ0 Q CLK SEL 3 18 VDD LE CLK 4 17 Q1 Pulldown CLK nCLK 5 16 nQ1 0 Pullup 0 Q0 nCLK PCLK 6 15 Q2 nQ0 nPCLK 7 14 nQ2 Pulldown PCLK 1 OE 8 13 1 Pullup nPCLK Q1 GND 9 12 Q3 10 11 VDD nQ3 nQ1 Pulldown CLK SEL Q2 ICS8543I nQ2 20-Lead TSSOP Q3 6.5mm x 4.4mm x 0.925mm nQ3 package body Pullup OE G Package Top View ICS8543BGI REVISION E NOVEMBER 15, 2012 1 2012 Integrated Device Technology, Inc.ICS8543I Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 9, 13 GND Power Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. 2 CLK EN Input Pullup When LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects PCLK/nPCLK inputs. 3 CLK SEL Input Pulldown When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK Input Pullup Inverting differential LVPECL clock input. Output enable. Controls enabling and disabling of outputs Q0/nQ0 through 8 OE Input Pullup Q3/nQ3. LVCMOS/LVTTL interface levels. 10, 18 V Power Positive supply pins. DD 11, 12 nQ3, Q3 Output Differential output pair. LVDS interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVDS interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVDS interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS8543BGI REVISION E NOVEMBER 15, 2012 2 2012 Integrated Device Technology, Inc.