8543BGLFT Renesas

GND ICS8543 Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer DATA SHEET General Description Features The ICS8543 is a low skew, high performance 1-to-4 Four differential LVDS output pairs Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Selectable differential CLK, nCLK or LVPECL clock inputs Differential Signaling (LVDS) the ICS8543 provides a low power, low CLK, nCLK pair can accept the following differential input levels: noise, solution for distributing clock signals over controlled LVPECL, LVDS, LVHSTL, SSTL, HCSL impedances of 100 . The ICS8543 has two selectable clock inputs. PCLK, nPCLK pair can accept the following differential input The CLK, nCLK pair can accept most standard differential input levels: LVPECL, CML, SSTL levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL Maximum output frequency: 800MHz input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous Translates any single-ended input signals to LVDS levels with resistor bias on nCLK input assertion/deassertion of the clock enable pin. Additive phase jitter, RMS: 0.164ps (typical) Guaranteed output and part-to-part skew characteristics make the ICS8543 ideal for those applications demanding well defined Output skew: 40ps (maximum) performance and repeatability. Part-to-part skew: 500ps (maximum) Propagation delay: 2.6ns (maximum) Full 3.3V supply mode 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Block Diagram Q0 GND 1 20 Pullup CLK EN D 2 19 nQ0 CLK EN Q CLK SEL 3 18 VDD LE CLK 4 17 Q1 Pulldown CLK 0 nCLK 5 16 Pullup 0 Q0 nQ1 nCLK PCLK 6 15 Q2 nQ0 Pulldown PCLK 1 nPCLK nQ2 7 14 1 Pullup nPCLK Q1 OE 8 13 nQ1 GND 9 12 Q3 Pulldown CLK SEL V 10 11 nQ3 DD Q2 nQ2 ICS8543 Q3 20-Lead TSSOP nQ3 Pullup 6.5mm x 4.4mm x 0.925mm OE package body G Package Top View ICS8543BG REVISION E DECEMBER 17, 2010 1 2010 Integrated Device Technology, Inc.ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 9, 13 GND Power Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When 2 CLK EN Input Pullup LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects PCLK, nPCLK inputs. 3 CLK SEL Input Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK Input Pullup Inverting differential LVPECL clock input. Output enable. Controls enabling and disabling of outputs Q 0:3 , nQ 0:3 . 8 OE Input Pullup LVCMOS/LVTTL interface levels. 10, 18 V Power Positive supply pins. DD 11, 12 nQ3, Q3 Output Differential output pair. LVDS interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVDS interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVDS interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS8543BG REVISION E DECEMBER 17, 2010 2 2010 Integrated Device Technology, Inc.