GND Low Skew, 1-to-4 LVCMOS/ LVTTL-to-LVDS 8545 Fanout Buffer Datasheet General Description Features The 8545 is a low skew, high performance 1-to-4 Four differential LVDS output pairs LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Two LVCMOS/LVTTL clock inputs to support redundant Differential Signaling (LVDS) the 8545 provides a low power, low or selectable frequency fanout applications noise, solution for distributing clock signals over controlled Maximum output frequency: 650MHz impedances of 100 . The 8545 accepts a LVCMOS/LVTTL input Translates LVCMOS/LVTTL input signals to LVDS levels level and translates it to 3.3V LVDS output levels. Output skew: 40ps (maximum) Guaranteed output and part-to-part skew characteristics make the Part-to-part skew: 500ps (maximum) 8545 ideal for those applications demanding well defined performance and repeatability. Propagation delay: 3.6ns (maximum) Additive phase jitter, RMS: 0.13ps (typical) Full 3.3Vsupply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment GND 1 20 Q0 Pullup CLK EN nD CLK EN 2 19 Q0 Q CLK SEL 3 18 VDD LE CLK1 4 17 Q1 Pulldown CLK1 0 0 Q0 nc 5 16 Q1 Q0 CLK2 6 15 Q2 Pulldown 1 CLK2 nc 1 7 14 Q2 Q1 OE 8 13 Q1 GND 9 12 Q3 Pulldown CLK SEL V 10 11 Q3 DD Q2 Q2 8545 Q3 20-Lead TSSOP Q3 Pullup 6.5mm x 4.4mm x 0.925mm package body OE G Package Top View 2015 Integrated Device Technology, Inc. 1 Revision C, December 8, 20158545 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 9, 13 GND Power Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. 2 CLK EN Input Pullup When LOW, Q outputs are forced low, Q outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK2 input. 3 CLK SEL Input Pulldown When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels. 4 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 5, 7 nc Unused No connect. 6 CLK2 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Q0/Q0 through 8 OE Input Pullup Q3/Q3. LVCMOS/LVTTL interface levels. 10, 18 V Power Positive supply pins. DD 11, 12 Q3, Q3 Output Differential output pair. LVDS interface levels. 14, 15 Q2, Q2 Output Differential output pair. LVDS interface levels. 16, 17 Q1, Q1 Output Differential output pair. LVDS interface levels. 19, 20 Q0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2015 Integrated Device Technology, Inc. 2 Revision C, December 8, 2015